EDAC/fsl_ddr: Pass down fsl_mc_pdata in ddr_in32() and ddr_out32()

Pass down fsl_mc_pdata in helper functions ddr_in32() and ddr_out32() to
prepare for adding iMX9 support. The iMX9 has a slightly different
register layout.

No functional change.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20241016-imx95_edac-v3-1-86ae6fc2756a@nxp.com

diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index d148d262d0d4de2e26f1adde9781193755b58c65..9924c6b81664809749f2fb66dfcfc374daad81da 100644 (file)
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -35,13 +35,17 @@ static u32 orig_ddr_err_disable;
 static u32 orig_ddr_err_sbe;
 static bool little_endian;
 
-static inline u32 ddr_in32(void __iomem *addr)
+static inline u32 ddr_in32(struct fsl_mc_pdata *pdata, unsigned int off)
 {
+       void __iomem *addr = pdata->mc_vbase + off;
+
        return little_endian ? ioread32(addr) : ioread32be(addr);
 }
 
-static inline void ddr_out32(void __iomem *addr, u32 value)
+static inline void ddr_out32(struct fsl_mc_pdata *pdata, unsigned int off, u32 value)
 {
+       void __iomem *addr = pdata->mc_vbase + off;
+
        if (little_endian)
                iowrite32(value, addr);
        else
@@ -60,7 +64,7 @@ static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
        struct mem_ctl_info *mci = to_mci(dev);
        struct fsl_mc_pdata *pdata = mci->pvt_info;
        return sprintf(data, "0x%08x",
-                      ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
+                      ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_HI));
 }
 
 static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
@@ -70,7 +74,7 @@ static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
        struct mem_ctl_info *mci = to_mci(dev);
        struct fsl_mc_pdata *pdata = mci->pvt_info;
        return sprintf(data, "0x%08x",
-                      ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
+                      ddr_in32(pdata, FSL_MC_DATA_ERR_INJECT_LO));
 }
 
 static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
@@ -80,7 +84,7 @@ static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
        struct mem_ctl_info *mci = to_mci(dev);
        struct fsl_mc_pdata *pdata = mci->pvt_info;
        return sprintf(data, "0x%08x",
-                      ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
+                      ddr_in32(pdata, FSL_MC_ECC_ERR_INJECT));
 }
 
 static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
@@ -97,7 +101,7 @@ static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
                if (rc)
                        return rc;
 
-               ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val);
+               ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_HI, val);
                return count;
        }
        return 0;
@@ -117,7 +121,7 @@ static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
                if (rc)
                        return rc;
 
-               ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val);
+               ddr_out32(pdata, FSL_MC_DATA_ERR_INJECT_LO, val);
                return count;
        }
        return 0;
@@ -137,7 +141,7 @@ static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
                if (rc)
                        return rc;
 
-               ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val);
+               ddr_out32(pdata, FSL_MC_ECC_ERR_INJECT, val);
                return count;
        }
        return 0;
@@ -286,7 +290,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
        int bad_data_bit;
        int bad_ecc_bit;
 
-       err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+       err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT);
        if (!err_detect)
                return;
 
@@ -295,14 +299,14 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
 
        /* no more processing if not ECC bit errors */
        if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
-               ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+               ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect);
                return;
        }
 
-       syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
+       syndrome = ddr_in32(pdata, FSL_MC_CAPTURE_ECC);
 
        /* Mask off appropriate bits of syndrome based on bus width */
-       bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
+       bus_width = (ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG) &
                     DSC_DBW_MASK) ? 32 : 64;
        if (bus_width == 64)
                syndrome &= 0xff;
@@ -310,8 +314,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
                syndrome &= 0xffff;
 
        err_addr = make64(
-               ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
-               ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
+               ddr_in32(pdata, FSL_MC_CAPTURE_EXT_ADDRESS),
+               ddr_in32(pdata, FSL_MC_CAPTURE_ADDRESS));
        pfn = err_addr >> PAGE_SHIFT;
 
        for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -320,8 +324,8 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
                        break;
        }
 
-       cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
-       cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
+       cap_high = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_HI);
+       cap_low = ddr_in32(pdata, FSL_MC_CAPTURE_DATA_LO);
 
        /*
         * Analyze single-bit errors on 64-bit wide buses
@@ -367,7 +371,7 @@ static void fsl_mc_check(struct mem_ctl_info *mci)
                                     row_index, 0, -1,
                                     mci->ctl_name, "");
 
-       ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
+       ddr_out32(pdata, FSL_MC_ERR_DETECT, err_detect);
 }
 
 static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
@@ -376,7 +380,7 @@ static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
        struct fsl_mc_pdata *pdata = mci->pvt_info;
        u32 err_detect;
 
-       err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
+       err_detect = ddr_in32(pdata, FSL_MC_ERR_DETECT);
        if (!err_detect)
                return IRQ_NONE;
 
@@ -396,7 +400,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
        u32 cs_bnds;
        int index;
 
-       sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+       sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG);
 
        sdtype = sdram_ctl & DSC_SDTYPE_MASK;
        if (sdram_ctl & DSC_RD_EN) {
@@ -444,7 +448,7 @@ static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
                csrow = mci->csrows[index];
                dimm = csrow->channels[0]->dimm;
 
-               cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
+               cs_bnds = ddr_in32(pdata, FSL_MC_CS_BNDS_0 +
                                   (index * FSL_MC_CS_BNDS_OFS));
 
                start = (cs_bnds & 0xffff0000) >> 16;
@@ -531,7 +535,7 @@ int fsl_mc_err_probe(struct platform_device *op)
                goto err;
        }
 
-       sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
+       sdram_ctl = ddr_in32(pdata, FSL_MC_DDR_SDRAM_CFG);
        if (!(sdram_ctl & DSC_ECC_EN)) {
                /* no ECC */
                pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -558,11 +562,11 @@ int fsl_mc_err_probe(struct platform_device *op)
        fsl_ddr_init_csrows(mci);
 
        /* store the original error disable bits */
-       orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
-       ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
+       orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE);
+       ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0);
 
        /* clear all error bits */
-       ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
+       ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0);
 
        res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups);
        if (res) {
@@ -571,15 +575,15 @@ int fsl_mc_err_probe(struct platform_device *op)
        }
 
        if (edac_op_state == EDAC_OPSTATE_INT) {
-               ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
+               ddr_out32(pdata, FSL_MC_ERR_INT_EN,
                          DDR_EIE_MBEE | DDR_EIE_SBEE);
 
                /* store the original error management threshold */
-               orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
+               orig_ddr_err_sbe = ddr_in32(pdata,
                                            FSL_MC_ERR_SBE) & 0xff0000;
 
                /* set threshold to 1 error per interrupt */
-               ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
+               ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000);
 
                /* register interrupts */
                pdata->irq = platform_get_irq(op, 0);
@@ -620,12 +624,12 @@ void fsl_mc_err_remove(struct platform_device *op)
        edac_dbg(0, "\n");
 
        if (edac_op_state == EDAC_OPSTATE_INT) {
-               ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
+               ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0);
        }
 
-       ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
+       ddr_out32(pdata, FSL_MC_ERR_DISABLE,
                  orig_ddr_err_disable);
-       ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
+       ddr_out32(pdata, FSL_MC_ERR_SBE, orig_ddr_err_sbe);
 
        edac_mc_del_mc(&op->dev);
        edac_mc_free(mci);