]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/amd/display: Don't use non-registered VUPDATE on DCE 6
authorTimur Kristóf <timur.kristof@gmail.com>
Mon, 25 Aug 2025 21:56:31 +0000 (23:56 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Sep 2025 21:04:35 +0000 (17:04 -0400)
The VUPDATE interrupt isn't registered on DCE 6, so don't try
to use that.

This fixes a page flip timeout after sleep/resume on DCE 6.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

index 38fa6319265e9e7db09db8c9d265a7453539962c..9dd2d1ed674d7cd92fa820a661ee839b6b9ae626 100644 (file)
@@ -3047,14 +3047,20 @@ static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
                                drm_warn(adev_to_drm(adev), "Failed to %s pflip interrupts\n",
                                         enable ? "enable" : "disable");
 
-                       if (enable) {
-                               if (amdgpu_dm_crtc_vrr_active(to_dm_crtc_state(acrtc->base.state)))
-                                       rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, true);
-                       } else
-                               rc = amdgpu_dm_crtc_set_vupdate_irq(&acrtc->base, false);
-
-                       if (rc)
-                               drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n", enable ? "en" : "dis");
+                       if (dc_supports_vrr(adev->dm.dc->ctx->dce_version)) {
+                               if (enable) {
+                                       if (amdgpu_dm_crtc_vrr_active(
+                                                       to_dm_crtc_state(acrtc->base.state)))
+                                               rc = amdgpu_dm_crtc_set_vupdate_irq(
+                                                       &acrtc->base, true);
+                               } else
+                                       rc = amdgpu_dm_crtc_set_vupdate_irq(
+                                                       &acrtc->base, false);
+
+                               if (rc)
+                                       drm_warn(adev_to_drm(adev), "Failed to %sable vupdate interrupt\n",
+                                               enable ? "en" : "dis");
+                       }
 
                        irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
                        /* During gpu-reset we disable and then enable vblank irq, so
index 45feb404b0979e498e0b8193b957bc54074621e1..466dccb355d7ba67e675aa7d03a1fd123c70722b 100644 (file)
@@ -317,13 +317,17 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
                        dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
                        sr_supported && vblank->config.disable_immediate)
                        drm_crtc_vblank_restore(crtc);
+       }
 
-               /* vblank irq on -> Only need vupdate irq in vrr mode */
-               if (amdgpu_dm_crtc_vrr_active(acrtc_state))
-                       rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
-       } else {
-               /* vblank irq off -> vupdate irq off */
-               rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
+       if (dc_supports_vrr(dm->dc->ctx->dce_version)) {
+               if (enable) {
+                       /* vblank irq on -> Only need vupdate irq in vrr mode */
+                       if (amdgpu_dm_crtc_vrr_active(acrtc_state))
+                               rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
+               } else {
+                       /* vblank irq off -> vupdate irq off */
+                       rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, false);
+               }
        }
 
        if (rc)