It could be just cmp 0xe instead of >>1 and cmp 0x7, with readable code.
Signed-off-by: Tomohiro Kusumi <tkusumi@tuxera.com>
Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
*/
static inline int ufshcd_get_lists_status(u32 reg)
{
- /*
- * The mask 0xFF is for the following HCS register bits
- * Bit Description
- * 0 Device Present
- * 1 UTRLRDY
- * 2 UTMRLRDY
- * 3 UCRDY
- * 4-7 reserved
- */
- return ((reg & 0xFF) >> 1) ^ 0x07;
+ return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
}
/**
#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
+#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
+ UTP_TASK_REQ_LIST_READY |\
+ UIC_COMMAND_READY)
+
enum {
PWR_OK = 0x0,
PWR_LOCAL = 0x01,