]> git.ipfire.org Git - thirdparty/openssl.git/commitdiff
riscv: Fix cpuid_obj asm checks for sm4/sm3
authorHongren Zheng <i@zenithal.me>
Fri, 24 May 2024 06:12:47 +0000 (14:12 +0800)
committerMatt Caswell <matt@openssl.org>
Fri, 12 Jul 2024 10:09:02 +0000 (11:09 +0100)
Similar to #22881 / #23752

Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Yang <kaishen.yy@antfin.com>
(Merged from https://github.com/openssl/openssl/pull/24486)

crypto/sm3/sm3_local.h
include/crypto/sm4_platform.h
providers/implementations/ciphers/cipher_sm4_ccm_hw.c
providers/implementations/ciphers/cipher_sm4_gcm_hw.c
providers/implementations/ciphers/cipher_sm4_hw.c
providers/implementations/ciphers/cipher_sm4_xts_hw.c

index d2845f96789672f201984bc3c914fde3c4882f30..a467cc98eb13effa7cc1f27e95f7533d79658a65 100644 (file)
@@ -39,7 +39,7 @@
 #  define HWSM3_CAPABLE (OPENSSL_armcap_P & ARMV8_SM3)
 void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
 # endif
-# if defined(__riscv) && __riscv_xlen == 64
+# if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 #  include "crypto/riscv_arch.h"
 #  define HWSM3_CAPABLE 1
 void ossl_hwsm3_block_data_order(SM3_CTX *c, const void *p, size_t num);
index 928dc17ff08382ecb4bc207cb198934840c66dfc..4d70d291450a1356a8ac69e6e311d40201c6073a 100644 (file)
@@ -38,7 +38,7 @@ static inline int vpsm4_ex_capable(void)
 #   define HWSM4_cbc_encrypt sm4_v8_cbc_encrypt
 #   define HWSM4_ecb_encrypt sm4_v8_ecb_encrypt
 #   define HWSM4_ctr32_encrypt_blocks sm4_v8_ctr32_encrypt_blocks
-#  elif defined(__riscv) && __riscv_xlen == 64
+#  elif defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 /* RV64 support */
 #   include "riscv_arch.h"
 /* Zvksed extension (vector crypto SM4). */
index 34f0e751e007d02a84a631fd410648ab99abf456..293bb69d64272507ed2f37eb4d9f9f7729da4173 100644 (file)
@@ -59,7 +59,7 @@ static const PROV_CCM_HW ccm_sm4 = {
     ossl_ccm_generic_gettag
 };
 
-#if defined(__riscv) && __riscv_xlen == 64
+#if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 # include "cipher_sm4_ccm_hw_rv64i.inc"
 #else
 const PROV_CCM_HW *ossl_prov_sm4_hw_ccm(size_t keybits)
index 06ca450782ff23b45799e688835b15599ac1de61..e3b4e9f58880791311f0273785f2c45bca4d0581 100644 (file)
@@ -89,7 +89,7 @@ static const PROV_GCM_HW sm4_gcm = {
     ossl_gcm_one_shot
 };
 
-#if defined(__riscv) && __riscv_xlen == 64
+#if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 # include "cipher_sm4_gcm_hw_rv64i.inc"
 #else
 const PROV_GCM_HW *ossl_prov_sm4_hw_gcm(size_t keybits)
index c4f2f97cccd8d87e2de111e9da5d04c25003ee88..70dc66ffae23332700451ea15ae83796d352801a 100644 (file)
@@ -134,7 +134,7 @@ const PROV_CIPHER_HW *ossl_prov_cipher_hw_sm4_##mode(size_t keybits)           \
     return &sm4_##mode;                                                        \
 }
 
-#if defined(__riscv) && __riscv_xlen == 64
+#if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 # include "cipher_sm4_hw_rv64i.inc"
 #else
 /* The generic case */
index 6cf58e851f5d43d12162b790c0872dee9854fea9..423598317d217675c5d3aae7ca05aaaa9dac1472 100644 (file)
@@ -89,7 +89,7 @@ static const PROV_CIPHER_HW sm4_generic_xts = {
     cipher_hw_sm4_xts_copyctx
 };
 
-#if defined(__riscv) && __riscv_xlen == 64
+#if defined(OPENSSL_CPUID_OBJ) && defined(__riscv) && __riscv_xlen == 64
 # include "cipher_sm4_xts_hw_rv64i.inc"
 #else
 const PROV_CIPHER_HW *ossl_prov_cipher_hw_sm4_xts(size_t keybits)