[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element...

	* config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF.
	* config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>):
	Use h_con constraint for operand 1.
	(*aarch64_fnma4_elt_from_dup<mode>): Likewise.
	(*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2.

From-SVN: r246189

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 82ab3d749c9fc7e03b2e1b3009ddf755f41fac38..e2e1015911f70eb34466d3f11b8cc2e89e8e2ce0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-03-16  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       * config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF.
+       * config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup<mode>):
+       Use h_con constraint for operand 1.
+       (*aarch64_fnma4_elt_from_dup<mode>): Likewise.
+       (*aarch64_mulx_elt_from_dup<mode>): Likewise for operand 2.
+
 2017-03-15  Jeff Law  <law@redhat.com>
 
        PR tree-optimization/71437

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 7ad3a76c8fa8bc28b8e0c6314958be7dfcf43457..8a3a551f73fd32c35774ed069e9448c5b0067019 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1647,7 +1647,7 @@
   [(set (match_operand:VMUL 0 "register_operand" "=w")
     (fma:VMUL
       (vec_duplicate:VMUL
-         (match_operand:<VEL> 1 "register_operand" "w"))
+         (match_operand:<VEL> 1 "register_operand" "<h_con>"))
       (match_operand:VMUL 2 "register_operand" "w")
       (match_operand:VMUL 3 "register_operand" "0")))]
   "TARGET_SIMD"
@@ -1726,7 +1726,7 @@
       (neg:VMUL
         (match_operand:VMUL 2 "register_operand" "w"))
       (vec_duplicate:VMUL
-       (match_operand:<VEL> 1 "register_operand" "w"))
+       (match_operand:<VEL> 1 "register_operand" "<h_con>"))
       (match_operand:VMUL 3 "register_operand" "0")))]
   "TARGET_SIMD"
   "fmls\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]"
@@ -3178,7 +3178,7 @@
        (unspec:VHSDF
         [(match_operand:VHSDF 1 "register_operand" "w")
          (vec_duplicate:VHSDF
-           (match_operand:<VEL> 2 "register_operand" "w"))]
+           (match_operand:<VEL> 2 "register_operand" "<h_con>"))]
         UNSPEC_FMULX))]
   "TARGET_SIMD"
   "fmulx\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";

diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 1ddf6ad9bc01fd6a36c6f5038a23714c1818974a..43be7fd361116d305b0300a814ffca82a9c44a88 100644 (file)
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -749,11 +749,11 @@
                                    (DF   "to_128") (V2DF  "to_64")])
 
 ;; For certain vector-by-element multiplication instructions we must
-;; constrain the HI cases to use only V0-V15.  This is covered by
+;; constrain the 16-bit cases to use only V0-V15.  This is covered by
 ;; the 'x' constraint.  All other modes may use the 'w' constraint.
 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
                         (V4HI "x") (V8HI "x")
-                        (V4HF "w") (V8HF "w")
+                        (V4HF "x") (V8HF "x")
                         (V2SF "w") (V4SF "w")
                         (V2DF "w") (DF "w")])