arm64: tegra: Resize aperture for the IGX PCIe C5 slot

Some discrete graphics cards such as the NVIDIA RTX A6000 support
resizable BARs. When connecting an A6000 card to the NVIDIA IGX Orin
platform, resizing the BAR1 aperture to 8GB fails because the current
device-tree configuration for the PCIe C5 slot cannot support this.
Fix this by updating the device-tree 'reg' and 'ranges' properties for
the PCIe C5 slot to support this.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20250116151903.476047-1-jonathanh@nvidia.com
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
index 36e8880537460611ffe64d37159b2db4015e7d90..9ce55b4d2de8921ff6ff2c70bad16eaee07e3f4f 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts
@@ -302,6 +302,16 @@
                };
 
                pcie@141a0000 {
+                       reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
+                              0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
+                              0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
+                              0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
+                              0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB)               */
+
+                       ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000      /* downstream I/O (1MB) */
+                                 0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000      /* non-prefetchable memory (128MB) */
+                                 0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>;    /* prefetchable memory (25088MB) */
+
                        status = "okay";
                        vddio-pex-ctl-supply = <&vdd_1v8_ls>;
                        phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,