crypto: x86/aes-xts - switch to new Intel CPU model defines

New CPU #defines encode vendor and family as well as model.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Eric Biggers <ebiggers@google.com>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Link: https://lore.kernel.org/r/20240520224620.9480-2-tony.luck@intel.com

diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index 5b25d2a58aeb008c1b891798d848eb0fd2dfbff9..ef031655b2d3f70f37c47b6d9bfc912dad7bb948 100644 (file)
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -1223,14 +1223,14 @@ DEFINE_XTS_ALG(vaes_avx10_512, "xts-aes-vaes-avx10_512", 800);
  * implementation with ymm registers (256-bit vectors) will be used instead.
  */
 static const struct x86_cpu_id zmm_exclusion_list[] = {
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_SKYLAKE_X },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_X },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_D },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_L },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_ICELAKE_NNPI },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE_L },
-       { .vendor = X86_VENDOR_INTEL, .family = 6, .model = INTEL_FAM6_TIGERLAKE },
+       X86_MATCH_VFM(INTEL_SKYLAKE_X,          0),
+       X86_MATCH_VFM(INTEL_ICELAKE_X,          0),
+       X86_MATCH_VFM(INTEL_ICELAKE_D,          0),
+       X86_MATCH_VFM(INTEL_ICELAKE,            0),
+       X86_MATCH_VFM(INTEL_ICELAKE_L,          0),
+       X86_MATCH_VFM(INTEL_ICELAKE_NNPI,       0),
+       X86_MATCH_VFM(INTEL_TIGERLAKE_L,        0),
+       X86_MATCH_VFM(INTEL_TIGERLAKE,          0),
        /* Allow Rocket Lake and later, and Sapphire Rapids and later. */
        /* Also allow AMD CPUs (starting with Zen 4, the first with AVX-512). */
        {},