arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch...

Add a node for the second TC9563 PCIe switch on PCIe1, which is connected
in cascade to the first TC9563 switch via the former's downstream port.

Two embedded Ethernet devices are present on one of the downstream
ports of this second switch as well. All the ports present in the
node represent the downstream ports and embedded endpoints.

The second TC9563 is powered up via the same LDO regulators as the first
one, and these can be controlled via two GPIOs, which are already present
as fixed regulators. This TC9563 can also be configured through I2C.

Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260317-industrial-mezzanine-pcie-v5-2-1358978517fe@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
index ad2795668ec88b6ee21bce8e43dc546ba6280bec..83908db335afa1ecc39555c4ee208385334b6809 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
@@ -150,6 +150,100 @@
        };
 };
 
+&pcie1 {
+       iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+                   <0x100 &apps_smmu 0x1c81 0x1>,
+                   <0x208 &apps_smmu 0x1c84 0x1>,
+                   <0x210 &apps_smmu 0x1c85 0x1>,
+                   <0x218 &apps_smmu 0x1c86 0x1>,
+                   <0x300 &apps_smmu 0x1c87 0x1>,
+                   <0x408 &apps_smmu 0x1c90 0x1>,
+                   <0x410 &apps_smmu 0x1c91 0x1>,
+                   <0x418 &apps_smmu 0x1c92 0x1>,
+                   <0x500 &apps_smmu 0x1c93 0x1>,
+                   <0x600 &apps_smmu 0x1c94 0x1>,
+                   <0x700 &apps_smmu 0x1c95 0x1>,
+                   <0x701 &apps_smmu 0x1c96 0x1>,
+                   <0x800 &apps_smmu 0x1c97 0x1>,
+                   <0x900 &apps_smmu 0x1c98 0x1>,
+                   <0x901 &apps_smmu 0x1c99 0x1>;
+};
+
+&pcie1_switch0_dsp1 {
+       #address-cells = <3>;
+       #size-cells = <2>;
+
+       pcie@0,0 {
+               compatible = "pci1179,0623";
+               reg = <0x30000 0x0 0x0 0x0 0x0>;
+               #address-cells = <3>;
+               #size-cells = <2>;
+
+               device_type = "pci";
+               ranges;
+               bus-range = <0x2 0xff>;
+
+               vddc-supply = <&vdd_ntn_0p9>;
+               vdd18-supply = <&vdd_ntn_1p8>;
+               vdd09-supply = <&vdd_ntn_0p9>;
+               vddio1-supply = <&vdd_ntn_1p8>;
+               vddio2-supply = <&vdd_ntn_1p8>;
+               vddio18-supply = <&vdd_ntn_1p8>;
+
+               i2c-parent = <&i2c1 0x77>;
+
+               resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
+
+               pinctrl-0 = <&pcie1_tc9563_resx_n>;
+               pinctrl-names = "default";
+
+               pcie@1,0 {
+                       reg = <0x40800 0x0 0x0 0x0 0x0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+                       ranges;
+                       bus-range = <0x3 0xff>;
+               };
+
+               pcie@2,0 {
+                       reg = <0x41000 0x0 0x0 0x0 0x0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       device_type = "pci";
+                       ranges;
+                       bus-range = <0x4 0xff>;
+               };
+
+               pcie@3,0 {
+                       reg = <0x41800 0x0 0x0 0x0 0x0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges;
+                       bus-range = <0x5 0xff>;
+
+                       pci@0,0 {
+                               reg = <0x50000 0x0 0x0 0x0 0x0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               device_type = "pci";
+                               ranges;
+                       };
+
+                       pci@0,1 {
+                               reg = <0x50100 0x0 0x0 0x0 0x0>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               device_type = "pci";
+                               ranges;
+                       };
+               };
+       };
+};
+
 &tlmm {
        pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
                pins = "gpio78";
@@ -181,6 +275,14 @@
                bias-pull-up;
        };
 
+       pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
+               pins = "gpio124";
+               function = "gpio";
+               bias-disable;
+               input-disable;
+               output-enable;
+       };
+
 };
 
 &wifi {

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index e3d2f01881ae05f17796f9c97f10b53cea50daff..cd54525e45e0f58c7c4d21b010422b55e5fbbb77 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -852,7 +852,7 @@
                pinctrl-0 = <&tc9563_resx_n>;
                pinctrl-names = "default";
 
-               pcie@1,0 {
+               pcie1_switch0_dsp1: pcie@1,0 {
                        reg = <0x20800 0x0 0x0 0x0 0x0>;
                        #address-cells = <3>;
                        #size-cells = <2>;