clk: meson: c3: pll: fix frac maximum value for hifi_pll

The fractional denominator of C3's hifi_pll fractional multiplier is
fixed to 100000.

Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock")
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c
index 32bd2ed9d304418883516e02da4d35b5b204b530..35fda31a19e218bb6db71346a264ec20e832382c 100644 (file)
--- a/drivers/clk/meson/c3-pll.c
+++ b/drivers/clk/meson/c3-pll.c
@@ -361,6 +361,7 @@ static struct clk_regmap hifi_pll_dco = {
                .range = &c3_gp0_pll_mult_range,
                .init_regs = c3_hifi_init_regs,
                .init_count = ARRAY_SIZE(c3_hifi_init_regs),
+               .frac_max = 100000,
        },
        .hw.init = &(struct clk_init_data) {
                .name = "hifi_pll_dco",