]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: toshiba: Fix pl011 and pl022 clocks
authorRob Herring <robh@kernel.org>
Mon, 26 Aug 2024 18:38:48 +0000 (13:38 -0500)
committerArnd Bergmann <arnd@arndb.de>
Thu, 5 Sep 2024 11:46:42 +0000 (11:46 +0000)
Arm Primecell blocks have a functional clock and a bus clock. The
Toshiba TMPV7708 only defines the bus clock (apb_pclk). Add the
"uartclk" and "sspclk" clocks to the PL011 and PL022 nodes,
respectively.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240826183848.1290957-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/arm64/boot/dts/toshiba/tmpv7708.dtsi

index b04829b3175de017ce36790722ecbfed024dd297..39806f0ae51337cddacbba60eb98e241f58f7cf7 100644 (file)
                        interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins>;
-                       clocks = <&pismu TMPV770X_CLK_PIUART0>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PIUART0>, <&pismu TMPV770X_CLK_PIUART0>;
+                       clock-names = "uartclk", "apb_pclk";
                        status = "disabled";
                };
 
                        interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart1_pins>;
-                       clocks = <&pismu TMPV770X_CLK_PIUART1>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PIUART1>, <&pismu TMPV770X_CLK_PIUART1>;
+                       clock-names = "uartclk", "apb_pclk";
                        status = "disabled";
                };
 
                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart2_pins>;
-                       clocks = <&pismu TMPV770X_CLK_PIUART2>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PIUART2>, <&pismu TMPV770X_CLK_PIUART2>;
+                       clock-names = "uartclk", "apb_pclk";
                        status = "disabled";
                };
 
                        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart3_pins>;
-                       clocks = <&pismu TMPV770X_CLK_PIUART2>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PIUART2>, <&pismu TMPV770X_CLK_PIUART2>;
+                       clock-names = "uartclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI1>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI1>, <&pismu TMPV770X_CLK_PISPI1>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI1>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI1>, <&pismu TMPV770X_CLK_PISPI1>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI2>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI2>, <&pismu TMPV770X_CLK_PISPI2>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI3>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI3>, <&pismu TMPV770X_CLK_PISPI3>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI4>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI4>, <&pismu TMPV770X_CLK_PISPI4>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI5>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI5>, <&pismu TMPV770X_CLK_PISPI5>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };
 
                        num-cs = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                       clocks = <&pismu TMPV770X_CLK_PISPI6>;
-                       clock-names = "apb_pclk";
+                       clocks = <&pismu TMPV770X_CLK_PISPI6>, <&pismu TMPV770X_CLK_PISPI6>;
+                       clock-names = "sspclk", "apb_pclk";
                        status = "disabled";
                };