drm/amd/pm: Add priority messages for SMU v13.0.6

Certain messages will processed with high priority by PMFW even if it
hasn't responded to a previous message. Send the priority message
regardless of the success/fail status of the previous message. Add
support on SMUv13.0.6 and SMUv13.0.12

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index d7a9e41820fae0f3878090ab5791a7e167df7c34..fba980fa5a015f643963c2d26b4336eaea7c9127 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -469,6 +469,7 @@ enum smu_feature_mask {
 /* Message category flags */
 #define SMU_MSG_VF_FLAG                        (1U << 0)
 #define SMU_MSG_RAS_PRI                        (1U << 1)
+#define SMU_MSG_NO_PRECHECK            (1U << 2)
 
 /* Firmware capability flags */
 #define SMU_FW_CAP_RAS_PRI             (1U << 0)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
index 02a455a31c2594c8995872cc55b9400de4d29958..476b7f062a245c46b3d627df703103c7cf37c24d 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
@@ -106,7 +106,7 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] =
        MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
        MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
        MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
-       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  SMU_MSG_RAS_PRI),
+       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),
        MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
        MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
        MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index a0ce108aab4450048915513cac6fec5be553930c..520bb7713f1495c27ced21d1faca903c3ef87d32 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -145,7 +145,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU
        MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
        MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
        MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
-       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  SMU_MSG_RAS_PRI),
+       MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),
        MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
        MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
        MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 59f9abd0f7b8cefa0c6bea45cd38decd425bf067..f532f7c6925975cb150584454b799f5d7123877c 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -256,11 +256,12 @@ static int __smu_cmn_ras_filter_msg(struct smu_context *smu,
 {
        struct amdgpu_device *adev = smu->adev;
        uint32_t flags, resp;
-       bool fed_status;
+       bool fed_status, pri;
 
        flags = __smu_cmn_get_msg_flags(smu, msg);
        *poll = true;
 
+       pri = !!(flags & SMU_MSG_NO_PRECHECK);
        /* When there is RAS fatal error, FW won't process non-RAS priority
         * messages. Don't allow any messages other than RAS priority messages.
         */
@@ -272,15 +273,18 @@ static int __smu_cmn_ras_filter_msg(struct smu_context *smu,
                                smu_get_message_name(smu, msg));
                        return -EACCES;
                }
+       }
 
+       if (pri || fed_status) {
                /* FW will ignore non-priority messages when a RAS fatal error
-                * is detected. Hence it is possible that a previous message
-                * wouldn't have got response. Allow to continue without polling
-                * for response status for priority messages.
+                * or reset condition is detected. Hence it is possible that a
+                * previous message wouldn't have got response. Allow to
+                * continue without polling for response status for priority
+                * messages.
                 */
                resp = RREG32(smu->resp_reg);
                dev_dbg(adev->dev,
-                       "Sending RAS priority message %s response status: %x",
+                       "Sending priority message %s response status: %x",
                        smu_get_message_name(smu, msg), resp);
                if (resp == 0)
                        *poll = false;