drm/i915/alpm: Move port alpm configuration

It is specified in Bspec where port alpm configuration is supposed to be
performed. Change accordingly.

v2:
  - drop HAS reference
  - ensure PORT_ALPM registers are not writen on older platform

Bspec: 68849
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-9-jouni.hogander@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index bbcf510b0c254afabeb616c8698b7492c8a3b7e1..dfdde8e4eabe46dc6c4bc7e6b6176a5bd1f1333b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -336,7 +336,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 {
        struct intel_display *display = to_intel_display(intel_dp);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-       enum port port = dp_to_dig_port(intel_dp)->base.port;
        u32 alpm_ctl;
 
        if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
@@ -368,23 +367,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
                                       pr_alpm_ctl);
                }
 
-               intel_de_write(display,
-                              PORT_ALPM_CTL(port),
-                              PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-                              PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
-                              PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
-                              PORT_ALPM_CTL_SILENCE_PERIOD(
-                                      intel_dp->alpm_parameters.silence_period_sym_clocks));
-
-               intel_de_write(display,
-                              PORT_ALPM_LFPS_CTL(port),
-                              PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
-                              PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
-                                      intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
-                              PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-                                      intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
-                              PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
-                                      intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms));
        } else {
                alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE |
                        ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines);
@@ -408,6 +390,36 @@ void intel_alpm_configure(struct intel_dp *intel_dp,
        intel_dp->alpm_parameters.transcoder = crtc_state->cpu_transcoder;
 }
 
+void intel_alpm_port_configure(struct intel_dp *intel_dp,
+                              const struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(intel_dp);
+       enum port port = dp_to_dig_port(intel_dp)->base.port;
+       u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
+
+       if (DISPLAY_VER(display) < 20)
+               return;
+
+       if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+               alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
+                       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
+                       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
+                       PORT_ALPM_CTL_SILENCE_PERIOD(
+                               intel_dp->alpm_parameters.silence_period_sym_clocks);
+               lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) |
+                       PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
+                               intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
+                       PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
+                               intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) |
+                       PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(
+                               intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms);
+       }
+
+       intel_de_write(display, PORT_ALPM_CTL(port), alpm_ctl_val);
+
+       intel_de_write(display, PORT_ALPM_LFPS_CTL(port), lfps_ctl_val);
+}
+
 void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
                                 struct intel_crtc *crtc)
 {

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 86f4d5ab1981b0f6ef92962cc55d64775be0a764..a861c20b5d79f152e464a30e3ff9e1bdcf08f69a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -27,6 +27,8 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
                            const struct intel_crtc_state *crtc_state);
 void intel_alpm_pre_plane_update(struct intel_atomic_state *state,
                                 struct intel_crtc *crtc);
+void intel_alpm_port_configure(struct intel_dp *intel_dp,
+                              const struct intel_crtc_state *crtc_state);
 void intel_alpm_post_plane_update(struct intel_atomic_state *state,
                                  struct intel_crtc *crtc);
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a82b93cbc81d2c06e5519c130a91b4411b5ca3d1..91118d115fd357aafc7c22644a694c77b736ebea 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -10,6 +10,7 @@
 
 #include "i915_reg.h"
 #include "i915_utils.h"
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3d47d0ed3c37b00b370cac2a8dce99eace6640d3..f9653fa667b748fa8d23e60266195aceb5079145 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3740,6 +3740,12 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 
        intel_ddi_buf_enable(encoder, intel_dp->DP);
        intel_dp->DP |= DDI_BUF_CTL_ENABLE;
+
+       /*
+        * 6.k If AUX-Less ALPM is going to be enabled
+        *     i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
+        */
+       intel_alpm_port_configure(intel_dp, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,