drm/i915/reg: fix PCH transcoder timing and data/link m/n style

Adhere to the style described at the top of i915_reg.h.

v2: Rebase with the indentation fixed (Ville)

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
Link: https://patchwork.freedesktop.org/patch/msgid/90b1145453050797d3030bc2e5e24da18f34bdda.1725974820.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1eede96a5415b8b10a68dc45c0e0af38da3e8b38..b617de6b692889c0f551c4bf2767988ff7deef0c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3160,33 +3160,76 @@
 /* transcoder */
 
 #define _PCH_TRANS_HTOTAL_A            0xe0000
+#define _PCH_TRANS_HTOTAL_B            0xe1000
+#define PCH_TRANS_HTOTAL(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
 #define  TRANS_HTOTAL_SHIFT            16
 #define  TRANS_HACTIVE_SHIFT           0
+
 #define _PCH_TRANS_HBLANK_A            0xe0004
+#define _PCH_TRANS_HBLANK_B            0xe1004
+#define PCH_TRANS_HBLANK(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
 #define  TRANS_HBLANK_END_SHIFT                16
 #define  TRANS_HBLANK_START_SHIFT      0
+
 #define _PCH_TRANS_HSYNC_A             0xe0008
+#define _PCH_TRANS_HSYNC_B             0xe1008
+#define PCH_TRANS_HSYNC(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
 #define  TRANS_HSYNC_END_SHIFT         16
 #define  TRANS_HSYNC_START_SHIFT       0
+
 #define _PCH_TRANS_VTOTAL_A            0xe000c
+#define _PCH_TRANS_VTOTAL_B            0xe100c
+#define PCH_TRANS_VTOTAL(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
 #define  TRANS_VTOTAL_SHIFT            16
 #define  TRANS_VACTIVE_SHIFT           0
+
 #define _PCH_TRANS_VBLANK_A            0xe0010
+#define _PCH_TRANS_VBLANK_B            0xe1010
+#define PCH_TRANS_VBLANK(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
 #define  TRANS_VBLANK_END_SHIFT                16
 #define  TRANS_VBLANK_START_SHIFT      0
+
 #define _PCH_TRANS_VSYNC_A             0xe0014
+#define _PCH_TRANS_VSYNC_B             0xe1014
+#define PCH_TRANS_VSYNC(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
 #define  TRANS_VSYNC_END_SHIFT         16
 #define  TRANS_VSYNC_START_SHIFT       0
+
 #define _PCH_TRANS_VSYNCSHIFT_A                0xe0028
+#define _PCH_TRANS_VSYNCSHIFT_B                0xe1028
+#define PCH_TRANS_VSYNCSHIFT(pipe)     _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
 
 #define _PCH_TRANSA_DATA_M1    0xe0030
+#define _PCH_TRANSB_DATA_M1    0xe1030
+#define PCH_TRANS_DATA_M1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
+
 #define _PCH_TRANSA_DATA_N1    0xe0034
+#define _PCH_TRANSB_DATA_N1    0xe1034
+#define PCH_TRANS_DATA_N1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
+
 #define _PCH_TRANSA_DATA_M2    0xe0038
+#define _PCH_TRANSB_DATA_M2    0xe1038
+#define PCH_TRANS_DATA_M2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
+
 #define _PCH_TRANSA_DATA_N2    0xe003c
+#define _PCH_TRANSB_DATA_N2    0xe103c
+#define PCH_TRANS_DATA_N2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
+
 #define _PCH_TRANSA_LINK_M1    0xe0040
+#define _PCH_TRANSB_LINK_M1    0xe1040
+#define PCH_TRANS_LINK_M1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
+
 #define _PCH_TRANSA_LINK_N1    0xe0044
+#define _PCH_TRANSB_LINK_N1    0xe1044
+#define PCH_TRANS_LINK_N1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
+
 #define _PCH_TRANSA_LINK_M2    0xe0048
+#define _PCH_TRANSB_LINK_M2    0xe1048
+#define PCH_TRANS_LINK_M2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
+
 #define _PCH_TRANSA_LINK_N2    0xe004c
+#define _PCH_TRANSB_LINK_N2    0xe104c
+#define PCH_TRANS_LINK_N2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
 
 /* Per-transcoder DIP controls (PCH) */
 #define _VIDEO_DIP_CTL_A         0xe0200
@@ -3292,40 +3335,6 @@
 
 #define HSW_STEREO_3D_CTL(dev_priv, trans)     _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A)
 
-#define _PCH_TRANS_HTOTAL_B            0xe1000
-#define _PCH_TRANS_HBLANK_B            0xe1004
-#define _PCH_TRANS_HSYNC_B             0xe1008
-#define _PCH_TRANS_VTOTAL_B            0xe100c
-#define _PCH_TRANS_VBLANK_B            0xe1010
-#define _PCH_TRANS_VSYNC_B             0xe1014
-#define _PCH_TRANS_VSYNCSHIFT_B                0xe1028
-
-#define PCH_TRANS_HTOTAL(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
-#define PCH_TRANS_HBLANK(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
-#define PCH_TRANS_HSYNC(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
-#define PCH_TRANS_VTOTAL(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
-#define PCH_TRANS_VBLANK(pipe)         _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
-#define PCH_TRANS_VSYNC(pipe)          _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
-#define PCH_TRANS_VSYNCSHIFT(pipe)     _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
-
-#define _PCH_TRANSB_DATA_M1    0xe1030
-#define _PCH_TRANSB_DATA_N1    0xe1034
-#define _PCH_TRANSB_DATA_M2    0xe1038
-#define _PCH_TRANSB_DATA_N2    0xe103c
-#define _PCH_TRANSB_LINK_M1    0xe1040
-#define _PCH_TRANSB_LINK_N1    0xe1044
-#define _PCH_TRANSB_LINK_M2    0xe1048
-#define _PCH_TRANSB_LINK_N2    0xe104c
-
-#define PCH_TRANS_DATA_M1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
-#define PCH_TRANS_DATA_N1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
-#define PCH_TRANS_DATA_M2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
-#define PCH_TRANS_DATA_N2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
-#define PCH_TRANS_LINK_M1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
-#define PCH_TRANS_LINK_N1(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
-#define PCH_TRANS_LINK_M2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
-#define PCH_TRANS_LINK_N2(pipe)        _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
-
 #define _PCH_TRANSACONF              0xf0008
 #define _PCH_TRANSBCONF              0xf1008
 #define PCH_TRANSCONF(pipe)    _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)