clk: renesas: r9a07g044: Add LCDC clock and reset entries

Add LCDC clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 66608696d2e2354e793eedb49871bdf280b9dd26..b5ddc50586700fd7370f3de250b37dc0eb8f72da 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -194,7 +194,7 @@ static const struct {
 };
 
 static const struct {
-       struct rzg2l_mod_clk common[62];
+       struct rzg2l_mod_clk common[65];
 #ifdef CONFIG_CLK_R9A07G054
        struct rzg2l_mod_clk drp[0];
 #endif
@@ -254,6 +254,12 @@ static const struct {
                                        0x558, 1),
                DEF_MOD("gpu_ace_clk",  R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
                                        0x558, 2),
+               DEF_COUPLED("lcdc_a",   R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
+                                       0x56c, 0),
+               DEF_COUPLED("lcdc_p",   R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
+                                       0x56c, 0),
+               DEF_MOD("lcdc_clk_d",   R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
+                                       0x56c, 1),
                DEF_MOD("ssi0_pclk",    R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
                                        0x570, 0),
                DEF_MOD("ssi0_sfr",     R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -349,6 +355,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
        DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
        DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
        DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+       DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
        DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
        DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
        DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),