drm/amd/amdgpu: enable perfcounter mgcg and repeater fgcg

enable perfcounter mgcg and repeater fgcg on gc 12.0.1

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 794e905204f437ed86f90d9830d491c8c39994ba..2d0b21348d64ad4536bf4a40df6995125c3894be 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3532,7 +3532,20 @@ static void gfx_v12_0_unset_safe_mode(struct amdgpu_device *adev,
 static void gfx_v12_0_update_perf_clk(struct amdgpu_device *adev,
                                      bool enable)
 {
-       /* TODO */
+       uint32_t def, data;
+
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
+               return;
+
+       def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+       if (enable)
+               data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
+       else
+               data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
+
+       if (def != data)
+               WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
 }
 
 static void gfx_v12_0_update_spm_vmid(struct amdgpu_device *adev,
@@ -3763,7 +3776,22 @@ static void gfx_v12_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
 static void gfx_v12_0_update_repeater_fgcg(struct amdgpu_device *adev,
                                           bool enable)
 {
-       /* TODO */
+       uint32_t def, data;
+
+       if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
+               return;
+
+       def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+       if (enable)
+               data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
+                                 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK);
+       else
+               data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK |
+                               RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK;
+
+       if (def != data)
+               WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
 }
 
 static void gfx_v12_0_update_sram_fgcg(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c
index 780e54b74979a3275f2a74edb21ebda8e69156b9..701056a865a4c3f4fc4e68b8dbbbe2c7111427ec 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc24.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc24.c
@@ -405,7 +405,9 @@ static int soc24_common_early_init(void *handle)
                        AMD_CG_SUPPORT_GFX_CGLS |
                        AMD_CG_SUPPORT_GFX_MGCG |
                        AMD_CG_SUPPORT_GFX_3D_CGCG |
-                       AMD_CG_SUPPORT_GFX_3D_CGLS;
+                       AMD_CG_SUPPORT_GFX_3D_CGLS |
+                       AMD_CG_SUPPORT_REPEATER_FGCG |
+                       AMD_CG_SUPPORT_GFX_PERF_CLK;
                adev->pg_flags = AMD_PG_SUPPORT_VCN |
                        AMD_PG_SUPPORT_JPEG |
                        AMD_PG_SUPPORT_VCN_DPG;