verification/rvgen: Generate each variable definition only once

If a variable appears multiple times in the specification, ltl2k generates
multiple variable definitions. This fails the build.

Make sure each variable is only defined once.

Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Cc: Gabriele Monaco <gmonaco@redhat.com>
Link: https://lore.kernel.org/107dcf0d0aa8482d5fbe0314c3138f61cd284e91.1752850449.git.namcao@linutronix.de
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>

diff --git a/tools/verification/rvgen/rvgen/ltl2k.py b/tools/verification/rvgen/rvgen/ltl2k.py
index 92e713861d86f4530a1c62bafdd628ead070c45e..59da351792ec453f7ef4681a70ec1c5c485f60f4 100644 (file)
--- a/tools/verification/rvgen/rvgen/ltl2k.py
+++ b/tools/verification/rvgen/rvgen/ltl2k.py
@@ -112,14 +112,16 @@ class ltl2k(generator.Monitor):
             if node.op.is_temporal():
                 continue
 
-            if isinstance(node.op, ltl2ba.Variable):
-                buf.append("\tbool %s = test_bit(LTL_%s, mon->atoms);" % (node, node.op.name))
-            elif isinstance(node.op, ltl2ba.AndOp):
+            if isinstance(node.op, ltl2ba.AndOp):
                 buf.append("\tbool %s = %s && %s;" % (node, node.op.left, node.op.right))
             elif isinstance(node.op, ltl2ba.OrOp):
                 buf.append("\tbool %s = %s || %s;" % (node, node.op.left, node.op.right))
             elif isinstance(node.op, ltl2ba.NotOp):
                 buf.append("\tbool %s = !%s;" % (node, node.op.child))
+
+        for atom in self.atoms:
+            buf.append("\tbool %s = test_bit(LTL_%s, mon->atoms);" % (atom.lower(), atom))
+
         buf.reverse()
 
         buf2 = []