aarch64: Add new test advsimd-copy.d

Only smov and the second dup variant were previously untested.  However,
the only test for umov was a disassembly test with -M no-aliases, and
the first dup variant was only tested in assembly in diagnostic.d with
the non-architectural syntax `dup v0.2d, v1.2d[0]`.

diff --git a/gas/testsuite/gas/aarch64/advsimd-copy.d b/gas/testsuite/gas/aarch64/advsimd-copy.d
new file mode 100644 (file)
index 0000000..59ade08
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-copy.d
@@ -0,0 +1,178 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+:   0e010400        dup     v0\.8b, v0\.b\[0\]
+ *[0-9a-f]+:   0e01041f        dup     v31\.8b, v0\.b\[0\]
+ *[0-9a-f]+:   0e0107e0        dup     v0\.8b, v31\.b\[0\]
+ *[0-9a-f]+:   0e1f0400        dup     v0\.8b, v0\.b\[15\]
+ *[0-9a-f]+:   0e020400        dup     v0\.4h, v0\.h\[0\]
+ *[0-9a-f]+:   0e02041f        dup     v31\.4h, v0\.h\[0\]
+ *[0-9a-f]+:   0e0207e0        dup     v0\.4h, v31\.h\[0\]
+ *[0-9a-f]+:   0e1e0400        dup     v0\.4h, v0\.h\[7\]
+ *[0-9a-f]+:   0e040400        dup     v0\.2s, v0\.s\[0\]
+ *[0-9a-f]+:   0e04041f        dup     v31\.2s, v0\.s\[0\]
+ *[0-9a-f]+:   0e0407e0        dup     v0\.2s, v31\.s\[0\]
+ *[0-9a-f]+:   0e1c0400        dup     v0\.2s, v0\.s\[3\]
+ *[0-9a-f]+:   4e010400        dup     v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+:   4e01041f        dup     v31\.16b, v0\.b\[0\]
+ *[0-9a-f]+:   4e0107e0        dup     v0\.16b, v31\.b\[0\]
+ *[0-9a-f]+:   4e1f0400        dup     v0\.16b, v0\.b\[15\]
+ *[0-9a-f]+:   4e020400        dup     v0\.8h, v0\.h\[0\]
+ *[0-9a-f]+:   4e02041f        dup     v31\.8h, v0\.h\[0\]
+ *[0-9a-f]+:   4e0207e0        dup     v0\.8h, v31\.h\[0\]
+ *[0-9a-f]+:   4e1e0400        dup     v0\.8h, v0\.h\[7\]
+ *[0-9a-f]+:   4e040400        dup     v0\.4s, v0\.s\[0\]
+ *[0-9a-f]+:   4e04041f        dup     v31\.4s, v0\.s\[0\]
+ *[0-9a-f]+:   4e0407e0        dup     v0\.4s, v31\.s\[0\]
+ *[0-9a-f]+:   4e1c0400        dup     v0\.4s, v0\.s\[3\]
+ *[0-9a-f]+:   4e080400        dup     v0\.2d, v0\.d\[0\]
+ *[0-9a-f]+:   4e08041f        dup     v31\.2d, v0\.d\[0\]
+ *[0-9a-f]+:   4e0807e0        dup     v0\.2d, v31\.d\[0\]
+ *[0-9a-f]+:   4e180400        dup     v0.2d, v0.d\[1\]
+ *[0-9a-f]+:   0e010c00        dup     v0\.8b, w0
+ *[0-9a-f]+:   0e010c1f        dup     v31\.8b, w0
+ *[0-9a-f]+:   0e010fe0        dup     v0\.8b, wzr
+ *[0-9a-f]+:   0e020c00        dup     v0\.4h, w0
+ *[0-9a-f]+:   0e020c1f        dup     v31\.4h, w0
+ *[0-9a-f]+:   0e020fe0        dup     v0\.4h, wzr
+ *[0-9a-f]+:   0e040c00        dup     v0\.2s, w0
+ *[0-9a-f]+:   0e040c1f        dup     v31\.2s, w0
+ *[0-9a-f]+:   0e040fe0        dup     v0\.2s, wzr
+ *[0-9a-f]+:   4e010c00        dup     v0\.16b, w0
+ *[0-9a-f]+:   4e010c1f        dup     v31\.16b, w0
+ *[0-9a-f]+:   4e010fe0        dup     v0\.16b, wzr
+ *[0-9a-f]+:   4e020c00        dup     v0\.8h, w0
+ *[0-9a-f]+:   4e020c1f        dup     v31\.8h, w0
+ *[0-9a-f]+:   4e020fe0        dup     v0\.8h, wzr
+ *[0-9a-f]+:   4e040c00        dup     v0\.4s, w0
+ *[0-9a-f]+:   4e040c1f        dup     v31\.4s, w0
+ *[0-9a-f]+:   4e040fe0        dup     v0\.4s, wzr
+ *[0-9a-f]+:   4e080c00        dup     v0\.2d, x0
+ *[0-9a-f]+:   4e080c1f        dup     v31\.2d, x0
+ *[0-9a-f]+:   4e080fe0        dup     v0\.2d, xzr
+ *[0-9a-f]+:   0e150c00        dup     v0\.8b, w0
+ *[0-9a-f]+:   4e180c00        dup     v0\.2d, x0
+ *[0-9a-f]+:   0e012c00        smov    w0, v0\.b\[0\]
+ *[0-9a-f]+:   0e012c1f        smov    wzr, v0\.b\[0\]
+ *[0-9a-f]+:   0e012fe0        smov    w0, v31\.b\[0\]
+ *[0-9a-f]+:   0e1f2c00        smov    w0, v0\.b\[15\]
+ *[0-9a-f]+:   0e022c00        smov    w0, v0\.h\[0\]
+ *[0-9a-f]+:   0e022c1f        smov    wzr, v0\.h\[0\]
+ *[0-9a-f]+:   0e022fe0        smov    w0, v31\.h\[0\]
+ *[0-9a-f]+:   0e1e2c00        smov    w0, v0\.h\[7\]
+ *[0-9a-f]+:   4e012c00        smov    x0, v0\.b\[0\]
+ *[0-9a-f]+:   4e012c1f        smov    xzr, v0\.b\[0\]
+ *[0-9a-f]+:   4e012fe0        smov    x0, v31\.b\[0\]
+ *[0-9a-f]+:   4e1f2c00        smov    x0, v0\.b\[15\]
+ *[0-9a-f]+:   4e022c00        smov    x0, v0\.h\[0\]
+ *[0-9a-f]+:   4e022c1f        smov    xzr, v0\.h\[0\]
+ *[0-9a-f]+:   4e022fe0        smov    x0, v31\.h\[0\]
+ *[0-9a-f]+:   4e1e2c00        smov    x0, v0\.h\[7\]
+ *[0-9a-f]+:   4e042c00        smov    x0, v0\.s\[0\]
+ *[0-9a-f]+:   4e042c1f        smov    xzr, v0\.s\[0\]
+ *[0-9a-f]+:   4e042fe0        smov    x0, v31\.s\[0\]
+ *[0-9a-f]+:   4e1c2c00        smov    x0, v0\.s\[3\]
+ *[0-9a-f]+:   0e013c00        umov    w0, v0\.b\[0\]
+ *[0-9a-f]+:   0e013c1f        umov    wzr, v0\.b\[0\]
+ *[0-9a-f]+:   0e013fe0        umov    w0, v31\.b\[0\]
+ *[0-9a-f]+:   0e1f3c00        umov    w0, v0\.b\[15\]
+ *[0-9a-f]+:   0e023c00        umov    w0, v0\.h\[0\]
+ *[0-9a-f]+:   0e023c1f        umov    wzr, v0\.h\[0\]
+ *[0-9a-f]+:   0e023fe0        umov    w0, v31\.h\[0\]
+ *[0-9a-f]+:   0e1e3c00        umov    w0, v0\.h\[7\]
+ *[0-9a-f]+:   0e043c00        mov     w0, v0\.s\[0\]
+ *[0-9a-f]+:   0e043c1f        mov     wzr, v0\.s\[0\]
+ *[0-9a-f]+:   0e043fe0        mov     w0, v31\.s\[0\]
+ *[0-9a-f]+:   0e1c3c00        mov     w0, v0\.s\[3\]
+ *[0-9a-f]+:   4e083c00        mov     x0, v0\.d\[0\]
+ *[0-9a-f]+:   4e083c1f        mov     xzr, v0\.d\[0\]
+ *[0-9a-f]+:   4e083fe0        mov     x0, v31\.d\[0\]
+ *[0-9a-f]+:   4e183c00        mov     x0, v0\.d\[1\]
+ *[0-9a-f]+:   0e043c00        mov     w0, v0\.s\[0\]
+ *[0-9a-f]+:   0e043c1f        mov     wzr, v0\.s\[0\]
+ *[0-9a-f]+:   0e043fe0        mov     w0, v31\.s\[0\]
+ *[0-9a-f]+:   0e1c3c00        mov     w0, v0\.s\[3\]
+ *[0-9a-f]+:   4e083c00        mov     x0, v0\.d\[0\]
+ *[0-9a-f]+:   4e083c1f        mov     xzr, v0\.d\[0\]
+ *[0-9a-f]+:   4e083fe0        mov     x0, v31\.d\[0\]
+ *[0-9a-f]+:   4e183c00        mov     x0, v0\.d\[1\]
+ *[0-9a-f]+:   4e011c00        mov     v0\.b\[0\], w0
+ *[0-9a-f]+:   4e011c1f        mov     v31\.b\[0\], w0
+ *[0-9a-f]+:   4e011fe0        mov     v0\.b\[0\], wzr
+ *[0-9a-f]+:   4e1f1c00        mov     v0\.b\[15\], w0
+ *[0-9a-f]+:   4e021c00        mov     v0\.h\[0\], w0
+ *[0-9a-f]+:   4e021c1f        mov     v31\.h\[0\], w0
+ *[0-9a-f]+:   4e021fe0        mov     v0\.h\[0\], wzr
+ *[0-9a-f]+:   4e1e1c00        mov     v0\.h\[7\], w0
+ *[0-9a-f]+:   4e041c00        mov     v0\.s\[0\], w0
+ *[0-9a-f]+:   4e041c1f        mov     v31\.s\[0\], w0
+ *[0-9a-f]+:   4e041fe0        mov     v0\.s\[0\], wzr
+ *[0-9a-f]+:   4e1c1c00        mov     v0\.s\[3\], w0
+ *[0-9a-f]+:   4e081c00        mov     v0\.d\[0\], x0
+ *[0-9a-f]+:   4e081c1f        mov     v31\.d\[0\], x0
+ *[0-9a-f]+:   4e081fe0        mov     v0\.d\[0\], xzr
+ *[0-9a-f]+:   4e181c00        mov     v0\.d\[1\], x0
+ *[0-9a-f]+:   4e011c00        mov     v0\.b\[0\], w0
+ *[0-9a-f]+:   4e011c1f        mov     v31\.b\[0\], w0
+ *[0-9a-f]+:   4e011fe0        mov     v0\.b\[0\], wzr
+ *[0-9a-f]+:   4e1f1c00        mov     v0\.b\[15\], w0
+ *[0-9a-f]+:   4e021c00        mov     v0\.h\[0\], w0
+ *[0-9a-f]+:   4e021c1f        mov     v31\.h\[0\], w0
+ *[0-9a-f]+:   4e021fe0        mov     v0\.h\[0\], wzr
+ *[0-9a-f]+:   4e1e1c00        mov     v0\.h\[7\], w0
+ *[0-9a-f]+:   4e041c00        mov     v0\.s\[0\], w0
+ *[0-9a-f]+:   4e041c1f        mov     v31\.s\[0\], w0
+ *[0-9a-f]+:   4e041fe0        mov     v0\.s\[0\], wzr
+ *[0-9a-f]+:   4e1c1c00        mov     v0\.s\[3\], w0
+ *[0-9a-f]+:   4e081c00        mov     v0\.d\[0\], x0
+ *[0-9a-f]+:   4e081c1f        mov     v31\.d\[0\], x0
+ *[0-9a-f]+:   4e081fe0        mov     v0\.d\[0\], xzr
+ *[0-9a-f]+:   4e181c00        mov     v0\.d\[1\], x0
+ *[0-9a-f]+:   6e010400        mov     v0\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+:   6e01041f        mov     v31\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+:   6e0107e0        mov     v0\.b\[0\], v31\.b\[0\]
+ *[0-9a-f]+:   6e1f0400        mov     v0\.b\[15\], v0\.b\[0\]
+ *[0-9a-f]+:   6e017c00        mov     v0\.b\[0\], v0\.b\[15\]
+ *[0-9a-f]+:   6e020400        mov     v0\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+:   6e02041f        mov     v31\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+:   6e0207e0        mov     v0\.h\[0\], v31\.h\[0\]
+ *[0-9a-f]+:   6e1e0400        mov     v0\.h\[7\], v0\.h\[0\]
+ *[0-9a-f]+:   6e027400        mov     v0\.h\[0\], v0\.h\[7\]
+ *[0-9a-f]+:   6e040400        mov     v0\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+:   6e04041f        mov     v31\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+:   6e0407e0        mov     v0\.s\[0\], v31\.s\[0\]
+ *[0-9a-f]+:   6e1c0400        mov     v0\.s\[3\], v0\.s\[0\]
+ *[0-9a-f]+:   6e046400        mov     v0\.s\[0\], v0\.s\[3\]
+ *[0-9a-f]+:   6e080400        mov     v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+:   6e08041f        mov     v31\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+:   6e0807e0        mov     v0\.d\[0\], v31\.d\[0\]
+ *[0-9a-f]+:   6e180400        mov     v0\.d\[1\], v0\.d\[0\]
+ *[0-9a-f]+:   6e084400        mov     v0\.d\[0\], v0\.d\[1\]
+ *[0-9a-f]+:   6e022c00        mov     v0\.h\[0\], v0\.h\[2\]
+ *[0-9a-f]+:   6e083c00        mov     v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+:   6e010400        mov     v0\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+:   6e01041f        mov     v31\.b\[0\], v0\.b\[0\]
+ *[0-9a-f]+:   6e0107e0        mov     v0\.b\[0\], v31\.b\[0\]
+ *[0-9a-f]+:   6e1f0400        mov     v0\.b\[15\], v0\.b\[0\]
+ *[0-9a-f]+:   6e017c00        mov     v0\.b\[0\], v0\.b\[15\]
+ *[0-9a-f]+:   6e020400        mov     v0\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+:   6e02041f        mov     v31\.h\[0\], v0\.h\[0\]
+ *[0-9a-f]+:   6e0207e0        mov     v0\.h\[0\], v31\.h\[0\]
+ *[0-9a-f]+:   6e1e0400        mov     v0\.h\[7\], v0\.h\[0\]
+ *[0-9a-f]+:   6e027400        mov     v0\.h\[0\], v0\.h\[7\]
+ *[0-9a-f]+:   6e040400        mov     v0\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+:   6e04041f        mov     v31\.s\[0\], v0\.s\[0\]
+ *[0-9a-f]+:   6e0407e0        mov     v0\.s\[0\], v31\.s\[0\]
+ *[0-9a-f]+:   6e1c0400        mov     v0\.s\[3\], v0\.s\[0\]
+ *[0-9a-f]+:   6e046400        mov     v0\.s\[0\], v0\.s\[3\]
+ *[0-9a-f]+:   6e080400        mov     v0\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+:   6e08041f        mov     v31\.d\[0\], v0\.d\[0\]
+ *[0-9a-f]+:   6e0807e0        mov     v0\.d\[0\], v31\.d\[0\]
+ *[0-9a-f]+:   6e180400        mov     v0\.d\[1\], v0\.d\[0\]
+ *[0-9a-f]+:   6e084400        mov     v0\.d\[0\], v0\.d\[1\]

diff --git a/gas/testsuite/gas/aarch64/advsimd-copy.s b/gas/testsuite/gas/aarch64/advsimd-copy.s
new file mode 100644 (file)
index 0000000..d061894
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-copy.s
@@ -0,0 +1,181 @@
+       dup     v0.8b, v0.b[0]
+       dup     v31.8b, v0.b[0]
+       dup     v0.8b, v31.b[0]
+       dup     v0.8b, v0.b[15]
+       dup     v0.4h, v0.h[0]
+       dup     v31.4h, v0.h[0]
+       dup     v0.4h, v31.h[0]
+       dup     v0.4h, v0.h[7]
+       dup     v0.2s, v0.s[0]
+       dup     v31.2s, v0.s[0]
+       dup     v0.2s, v31.s[0]
+       dup     v0.2s, v0.s[3]
+       dup     v0.16b, v0.b[0]
+       dup     v31.16b, v0.b[0]
+       dup     v0.16b, v31.b[0]
+       dup     v0.16b, v0.b[15]
+       dup     v0.8h, v0.h[0]
+       dup     v31.8h, v0.h[0]
+       dup     v0.8h, v31.h[0]
+       dup     v0.8h, v0.h[7]
+       dup     v0.4s, v0.s[0]
+       dup     v31.4s, v0.s[0]
+       dup     v0.4s, v31.s[0]
+       dup     v0.4s, v0.s[3]
+       dup     v0.2d, v0.d[0]
+       dup     v31.2d, v0.d[0]
+       dup     v0.2d, v31.d[0]
+       dup     v0.2d, v0.d[1]
+
+       dup     v0.8b, w0
+       dup     v31.8b, w0
+       dup     v0.8b, wzr
+       dup     v0.4h, w0
+       dup     v31.4h, w0
+       dup     v0.4h, wzr
+       dup     v0.2s, w0
+       dup     v31.2s, w0
+       dup     v0.2s, wzr
+       dup     v0.16b, w0
+       dup     v31.16b, w0
+       dup     v0.16b, wzr
+       dup     v0.8h, w0
+       dup     v31.8h, w0
+       dup     v0.8h, wzr
+       dup     v0.4s, w0
+       dup     v31.4s, w0
+       dup     v0.4s, wzr
+       dup     v0.2d, x0
+       dup     v31.2d, x0
+       dup     v0.2d, xzr
+// Unspecified bits in imm5 (20..16) are ignored but should be set to zero by
+// an assembler.  This tests disassembly when the ignored bits are nonzero.
+       .inst   0x0e150c00
+       .inst   0x4e180c00
+
+       smov    w0, v0.b[0]
+       smov    wzr, v0.b[0]
+       smov    w0, v31.b[0]
+       smov    w0, v0.b[15]
+       smov    w0, v0.h[0]
+       smov    wzr, v0.h[0]
+       smov    w0, v31.h[0]
+       smov    w0, v0.h[7]
+       smov    x0, v0.b[0]
+       smov    xzr, v0.b[0]
+       smov    x0, v31.b[0]
+       smov    x0, v0.b[15]
+       smov    x0, v0.h[0]
+       smov    xzr, v0.h[0]
+       smov    x0, v31.h[0]
+       smov    x0, v0.h[7]
+       smov    x0, v0.s[0]
+       smov    xzr, v0.s[0]
+       smov    x0, v31.s[0]
+       smov    x0, v0.s[3]
+
+       umov    w0, v0.b[0]
+       umov    wzr, v0.b[0]
+       umov    w0, v31.b[0]
+       umov    w0, v0.b[15]
+       umov    w0, v0.h[0]
+       umov    wzr, v0.h[0]
+       umov    w0, v31.h[0]
+       umov    w0, v0.h[7]
+       umov    w0, v0.s[0]
+       umov    wzr, v0.s[0]
+       umov    w0, v31.s[0]
+       umov    w0, v0.s[3]
+       umov    x0, v0.d[0]
+       umov    xzr, v0.d[0]
+       umov    x0, v31.d[0]
+       umov    x0, v0.d[1]
+
+       mov     w0, v0.s[0]
+       mov     wzr, v0.s[0]
+       mov     w0, v31.s[0]
+       mov     w0, v0.s[3]
+       mov     x0, v0.d[0]
+       mov     xzr, v0.d[0]
+       mov     x0, v31.d[0]
+       mov     x0, v0.d[1]
+
+       ins     v0.b[0], w0
+       ins     v31.b[0], w0
+       ins     v0.b[0], wzr
+       ins     v0.b[15], w0
+       ins     v0.h[0], w0
+       ins     v31.h[0], w0
+       ins     v0.h[0], wzr
+       ins     v0.h[7], w0
+       ins     v0.s[0], w0
+       ins     v31.s[0], w0
+       ins     v0.s[0], wzr
+       ins     v0.s[3], w0
+       ins     v0.d[0], x0
+       ins     v31.d[0], x0
+       ins     v0.d[0], xzr
+       ins     v0.d[1], x0
+
+       mov     v0.b[0], w0
+       mov     v31.b[0], w0
+       mov     v0.b[0], wzr
+       mov     v0.b[15], w0
+       mov     v0.h[0], w0
+       mov     v31.h[0], w0
+       mov     v0.h[0], wzr
+       mov     v0.h[7], w0
+       mov     v0.s[0], w0
+       mov     v31.s[0], w0
+       mov     v0.s[0], wzr
+       mov     v0.s[3], w0
+       mov     v0.d[0], x0
+       mov     v31.d[0], x0
+       mov     v0.d[0], xzr
+       mov     v0.d[1], x0
+
+       ins     v0.b[0], v0.b[0]
+       ins     v31.b[0], v0.b[0]
+       ins     v0.b[0], v31.b[0]
+       ins     v0.b[15], v0.b[0]
+       ins     v0.b[0], v0.b[15]
+       ins     v0.h[0], v0.h[0]
+       ins     v31.h[0], v0.h[0]
+       ins     v0.h[0], v31.h[0]
+       ins     v0.h[7], v0.h[0]
+       ins     v0.h[0], v0.h[7]
+       ins     v0.s[0], v0.s[0]
+       ins     v31.s[0], v0.s[0]
+       ins     v0.s[0], v31.s[0]
+       ins     v0.s[3], v0.s[0]
+       ins     v0.s[0], v0.s[3]
+       ins     v0.d[0], v0.d[0]
+       ins     v31.d[0], v0.d[0]
+       ins     v0.d[0], v31.d[0]
+       ins     v0.d[1], v0.d[0]
+       ins     v0.d[0], v0.d[1]
+// Unspecified bits in imm4 (14..11) are ignored but should be set to zero by
+// an assembler.  This tests disassembly when the ignored bits are nonzero.
+       .inst   0x6e022c00
+       .inst   0x6e083c00
+
+       mov     v0.b[0], v0.b[0]
+       mov     v31.b[0], v0.b[0]
+       mov     v0.b[0], v31.b[0]
+       mov     v0.b[15], v0.b[0]
+       mov     v0.b[0], v0.b[15]
+       mov     v0.h[0], v0.h[0]
+       mov     v31.h[0], v0.h[0]
+       mov     v0.h[0], v31.h[0]
+       mov     v0.h[7], v0.h[0]
+       mov     v0.h[0], v0.h[7]
+       mov     v0.s[0], v0.s[0]
+       mov     v31.s[0], v0.s[0]
+       mov     v0.s[0], v31.s[0]
+       mov     v0.s[3], v0.s[0]
+       mov     v0.s[0], v0.s[3]
+       mov     v0.d[0], v0.d[0]
+       mov     v31.d[0], v0.d[0]
+       mov     v0.d[0], v31.d[0]
+       mov     v0.d[1], v0.d[0]
+       mov     v0.d[0], v0.d[1]