u32 val;
int alt_shift = (pin % 8) * 4;
int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
- unsigned long flags;
-
- spin_lock_irqsave(&bank->lock, flags);
val = readl_relaxed(bank->base + alt_offset);
val &= GENMASK(alt_shift + 3, alt_shift);
val = readl_relaxed(bank->base + STM32_GPIO_MODER);
val &= GENMASK(pin * 2 + 1, pin * 2);
*mode = val >> (pin * 2);
-
- spin_unlock_irqrestore(&bank->lock, flags);
}
static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
val &= BIT(offset);
- spin_unlock_irqrestore(&bank->lock, flags);
-
return (val >> offset);
}
static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
- spin_unlock_irqrestore(&bank->lock, flags);
-
return (val >> (offset * 2));
}
static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
unsigned int offset)
{
- unsigned long flags;
u32 val;
- spin_lock_irqsave(&bank->lock, flags);
-
val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
val &= GENMASK(offset * 2 + 1, offset * 2);
- spin_unlock_irqrestore(&bank->lock, flags);
-
return (val >> (offset * 2));
}
static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
unsigned int offset, bool dir)
{
- unsigned long flags;
u32 val;
- spin_lock_irqsave(&bank->lock, flags);
-
if (dir)
val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
BIT(offset));
val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
BIT(offset));
- spin_unlock_irqrestore(&bank->lock, flags);
-
return val;
}