drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link training

DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared DOWNSPREAD_CTRL register to 0 before start link training. At rare
case that DP MSA timing parameters may be mis-interpreted by the sink
which causes audio sampling rate be calculated wrongly and cause audio
did not work at sink if DOWNSPREAD_CTRL register is not cleared to 0.

Changes in v2:
1) fix spelling at commit text
2) merge ssc variable into encoding[0]

Changes in v3:
-- correct spelling of DOWNSPREAD_CTRL
-- replace err with len of ssize_t

Changes in v4:
-- split into 2 patches

Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support")
Patchwork: https://patchwork.freedesktop.org/patch/502532/
Link: https://lore.kernel.org/r/1662999830-13916-2-git-send-email-quic_khsieh@quicinc.com
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 3854c9f1f7e9020288d350f3b37311a748a1e341..dd26ca651a0544ba349df14025157fdeacfa5845 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1243,8 +1243,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
 {
        int ret = 0;
        const u8 *dpcd = ctrl->panel->dpcd;
-       u8 encoding = DP_SET_ANSI_8B10B;
-       u8 ssc;
+       u8 encoding[] = { 0, DP_SET_ANSI_8B10B };
        u8 assr;
        struct dp_link_info link_info = {0};
 
@@ -1256,13 +1255,11 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,
 
        dp_aux_link_configure(ctrl->aux, &link_info);
 
-       if (drm_dp_max_downspread(dpcd)) {
-               ssc = DP_SPREAD_AMP_0_5;
-               drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, &ssc, 1);
-       }
+       if (drm_dp_max_downspread(dpcd))
+               encoding[0] |= DP_SPREAD_AMP_0_5;
 
-       drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
-                               &encoding, 1);
+       /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */
+       drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
 
        if (drm_dp_alternate_scrambler_reset_cap(dpcd)) {
                assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;