arm64/sysreg: Get rid of the TCR2_EL1x SysregFields

TCR2_EL1x is a pretty bizarre construct, as it is shared between
TCR2_EL1 and TCR2_EL12. But the latter is obviously only an
accessor to the former.

In order to make things more consistent, upgrade TCR2_EL1x to
a full-blown sysreg definition for TCR2_EL1, and describe TCR2_EL12
as a mapping to TCR2_EL1.

This results in a couple of minor changes to the actual code.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241219173351.1123087-3-maz@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7c5b53f179a42666d4326c441b23a5b4106b4347..3229238a56acc8adc8d2fa9e99afb9da5838affc 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2375,7 +2375,7 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused)
 #ifdef CONFIG_ARM64_POE
 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused)
 {
-       sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE);
+       sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE);
        sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE);
 }
 #endif

diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index 8c5d7990e5b31207e9ded0da9319591d3c69e47f..0905b8778a9bb9380cf9d191d89d465328d616f6 100644 (file)
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -111,7 +111,7 @@ static bool s1pie_enabled(struct kvm_vcpu *vcpu, enum trans_regime regime)
                return vcpu_read_sys_reg(vcpu, TCR2_EL2) & TCR2_EL2_PIE;
        case TR_EL10:
                return  (__vcpu_sys_reg(vcpu, HCRX_EL2) & HCRX_EL2_TCR2En) &&
-                       (__vcpu_sys_reg(vcpu, TCR2_EL1) & TCR2_EL1x_PIE);
+                       (__vcpu_sys_reg(vcpu, TCR2_EL1) & TCR2_EL1_PIE);
        default:
                BUG();
        }
@@ -140,8 +140,8 @@ static void compute_s1poe(struct kvm_vcpu *vcpu, struct s1_walk_info *wi)
                }
 
                val = __vcpu_sys_reg(vcpu, TCR2_EL1);
-               wi->poe = val & TCR2_EL1x_POE;
-               wi->e0poe = val & TCR2_EL1x_E0POE;
+               wi->poe = val & TCR2_EL1_POE;
+               wi->e0poe = val & TCR2_EL1_E0POE;
        }
 }
 

diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index b8edc5765441e60f63ff08b4cf88a224374539b7..fb30c8804f87b003c8eb4c8d5f7cc9575873e051 100644 (file)
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -501,7 +501,7 @@ alternative_else_nop_endif
 #ifdef CONFIG_ARM64_HAFT
        cmp     x9, ID_AA64MMFR1_EL1_HAFDBS_HAFT
        b.lt    1f
-       orr     tcr2, tcr2, TCR2_EL1x_HAFT
+       orr     tcr2, tcr2, TCR2_EL1_HAFT
 #endif /* CONFIG_ARM64_HAFT */
 1:
 #endif /* CONFIG_ARM64_HW_AFDBM */
@@ -532,7 +532,8 @@ alternative_else_nop_endif
 #undef PTE_MAYBE_NG
 #undef PTE_MAYBE_SHARED
 
-       orr     tcr2, tcr2, TCR2_EL1x_PIE
+       orr     tcr2, tcr2, TCR2_EL1_PIE
+       msr     REG_TCR2_EL1, x0
 
 .Lskip_indirection:
 

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index da3f02cdf1052ab9301a8bbdc0d6bcc9b4386b79..64712e00787f936327d0ecf029886e1e588e79a1 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3000,7 +3000,7 @@ Sysreg    TTBR1_EL1       3       0       2       0       1
 Fields TTBRx_EL1
 EndSysreg
 
-SysregFields   TCR2_EL1x
+Sysreg TCR2_EL1        3       0       2       0       3
 Res0   63:16
 Field  15      DisCH1
 Field  14      DisCH0
@@ -3014,14 +3014,10 @@ Field   3       POE
 Field  2       E0POE
 Field  1       PIE
 Field  0       PnCH
-EndSysregFields
-
-Sysreg TCR2_EL1        3       0       2       0       3
-Fields TCR2_EL1x
 EndSysreg
 
 Sysreg TCR2_EL12       3       5       2       0       3
-Fields TCR2_EL1x
+Mapping        TCR2_EL1
 EndSysreg
 
 Sysreg TCR2_EL2        3       4       2       0       3