net: stmmac: rk: remove incorrect _DLY_DISABLE bit definition

The RK3328 GMAC clock delay macros define enable/disable controls for
TX and RX clock delay. While the TX definitions are correct, the
RXCLK_DLY_DISABLE macro incorrectly clears bit 0.

The macros RK3328_GMAC_TXCLK_DLY_DISABLE and
RK3328_GMAC_RXCLK_DLY_DISABLE are not referenced anywhere
in the driver code. Remove them to clean up unused definitions.

No functional change.

Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/20250826102219.49656-1-alok.a.tiwari@oracle.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 9fc41207cc459313e575a2b00236b82611ad9603..266c5337923659dd9b5e5c7cd5b460d8deac3b8f 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -556,9 +556,7 @@ static const struct rk_gmac_ops rk3308_ops = {
 #define RK3328_GMAC_RMII_MODE          GRF_BIT(9)
 #define RK3328_GMAC_RMII_MODE_CLR      GRF_CLR_BIT(9)
 #define RK3328_GMAC_TXCLK_DLY_ENABLE   GRF_BIT(0)
-#define RK3328_GMAC_TXCLK_DLY_DISABLE  GRF_CLR_BIT(0)
 #define RK3328_GMAC_RXCLK_DLY_ENABLE   GRF_BIT(1)
-#define RK3328_GMAC_RXCLK_DLY_DISABLE  GRF_CLR_BIT(0)
 
 /* RK3328_GRF_MACPHY_CON1 */
 #define RK3328_MACPHY_RMII_MODE                GRF_BIT(9)