"__ARM_FEATURE_SME_F16F16", pfile);
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
+ aarch64_def_or_undef (AARCH64_HAVE_ISA (SME2p1),
+ "__ARM_FEATURE_SME2p1", pfile);
/* Not for ACLE, but required to keep "float.h" correct if we switch
target between implementations that do or do not support ARMv8.2-A
AARCH64_OPT_FMV_EXTENSION("sme2", SME2, (SME), (), (), "sme2")
+AARCH64_OPT_EXTENSION("sme2p1", SME2p1, (SME2), (), (), "sme2p1")
+
AARCH64_OPT_EXTENSION("sme-b16b16", SME_B16B16, (SME2, SVE_B16B16), (), (), "")
AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "")
;; -------------------------------------------------------------------------
;; Includes:
;; - MOVA
+;; - MOVAZ
;; -------------------------------------------------------------------------
(define_insn "@aarch64_sme_<optab><v_int_container><mode>"
"mova\t%0.q, %2/m, za%3<hv>.q[%w4, 0]"
)
+(define_insn "@aarch64_sme_<optab><v_int_container><mode>"
+ [(set (match_operand:SVE_FULL 0 "register_operand" "=w")
+ (unspec:SVE_FULL
+ [(reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:DI 1 "const_int_operand")
+ (match_operand:SI 2 "register_operand" "Ucj")
+ (const_int 0)]
+ SME_READZ_HV))
+ (set (reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (unspec:<V_INT_CONTAINER>
+ [(reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (match_dup 2)
+ (const_int 1)]
+ SME_READZ_HV))]
+ "TARGET_STREAMING_SME2p1"
+ "movaz\t%0.<Vetype>, za%1<hv>.<Vetype>[%w2, 0]"
+)
+
+(define_insn "*aarch64_sme_<optab><v_int_container><mode>_plus"
+ [(set (match_operand:SVE_FULL 0 "register_operand" "=w")
+ (unspec:SVE_FULL
+ [(reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:DI 1 "const_int_operand")
+ (plus:SI (match_operand:SI 2 "register_operand" "Ucj")
+ (match_operand:SI 3 "const_int_operand"))
+ (const_int 0)]
+ SME_READZ_HV))
+ (set (reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (unspec:<V_INT_CONTAINER>
+ [(reg:<V_INT_CONTAINER> ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (plus:SI (match_dup 2)
+ (match_dup 3))
+ (const_int 1)]
+ SME_READZ_HV))]
+ "TARGET_STREAMING_SME2p1
+ && UINTVAL (operands[3]) < 128 / <elem_bits>"
+ "movaz\t%0.<Vetype>, za%1<hv>.<Vetype>[%w2, %3]"
+)
+
+(define_insn "@aarch64_sme_<optab><VNx1TI_ONLY:mode><SVE_FULL:mode>"
+ [(set (match_operand:SVE_FULL 0 "register_operand" "=w")
+ (unspec:SVE_FULL
+ [(reg:VNx1TI_ONLY ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:DI 1 "const_int_operand")
+ (match_operand:SI 2 "register_operand" "Ucj")
+ (const_int 0)]
+ SME_READZ_HV))
+ (set (reg:VNx1TI_ONLY ZA_REGNUM)
+ (unspec:VNx1TI_ONLY
+ [(reg:VNx1TI_ONLY ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (match_dup 2)
+ (const_int 0)]
+ SME_READZ_HV))]
+ "TARGET_STREAMING_SME2p1"
+ "movaz\t%0.q, za%1<hv>.q[%w2, 0]"
+)
+
(define_insn "@aarch64_sme_<optab><v_int_container><mode>"
[(set (reg:<V_INT_CONTAINER> ZA_REGNUM)
(unspec:<V_INT_CONTAINER>
;; -------------------------------------------------------------------------
;; Includes:
;; - MOVA
+;; - MOVAZ
;; -------------------------------------------------------------------------
(define_insn "@aarch64_sme_<optab><mode><mode>"
}
)
+(define_insn "@aarch64_sme_<optab><mode><mode>"
+ [(set (match_operand:SVE_FULLx24 0 "aligned_register_operand" "=Uw<vector_count>")
+ (unspec:SVE_FULLx24
+ [(reg:SVE_FULLx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:DI 1 "const_int_operand")
+ (match_operand:SI 2 "register_operand" "Ucj")
+ (const_int 0)]
+ SME_READZ_HV))
+ (set (reg:SVE_FULLx24 ZA_REGNUM)
+ (unspec:SVE_FULLx24
+ [(reg:SVE_FULLx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (match_dup 2)
+ (const_int 1)]
+ SME_READZ_HV))]
+ "TARGET_STREAMING_SME2p1"
+ {
+ operands[3] = GEN_INT (<vector_count> - 1);
+ return "movaz\t%0, za%1<hv>.<Vetype>[%w2, 0:%3]";
+ }
+)
+
+(define_insn "*aarch64_sme_<optab><mode><mode>_plus"
+ [(set (match_operand:SVE_FULLx24 0 "aligned_register_operand" "=Uw<vector_count>")
+ (unspec:SVE_FULLx24
+ [(reg:SVE_FULLx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:DI 1 "const_int_operand")
+ (plus:SI
+ (match_operand:SI 2 "register_operand" "Ucj")
+ (match_operand:SI 3 "const_int_operand"))
+ (const_int 0)]
+ SME_READZ_HV))
+ (set (reg:SVE_FULLx24 ZA_REGNUM)
+ (unspec:SVE_FULLx24
+ [(reg:SVE_FULLx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (plus:SI
+ (match_dup 2)
+ (match_dup 3))
+ (const_int 1)]
+ SME_READZ_HV))]
+ "TARGET_STREAMING_SME2p1
+ && UINTVAL (operands[3]) % <vector_count> == 0
+ && UINTVAL (operands[3]) < 128 / <elem_bits>"
+ {
+ operands[4] = GEN_INT (INTVAL (operands[3]) + <vector_count> - 1);
+ return "movaz\t%0, za%1<hv>.<Vetype>[%w2, %3:%4]";
+ }
+)
+
(define_insn "@aarch64_sme_read<mode>"
[(set (match_operand:SVE_DIx24 0 "aligned_register_operand" "=Uw<vector_count>")
(unspec:SVE_DIx24
"mova\t%0, za.d[%w1, %2, vgx<vector_count>]"
)
+(define_insn "@aarch64_sme_readz<mode>"
+ [(set (match_operand:SVE_DIx24 0 "aligned_register_operand" "=Uw<vector_count>")
+ (unspec:SVE_DIx24
+ [(reg:SVE_DIx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_operand:SI 1 "register_operand" "Uci")
+ (const_int 0)]
+ UNSPEC_SME_READZ))
+ (set (reg:SVE_DIx24 ZA_REGNUM)
+ (unspec:SVE_DIx24
+ [(reg:SVE_DIx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (match_dup 1)
+ (const_int 1)]
+ UNSPEC_SME_READZ))]
+ "TARGET_STREAMING_SME2p1"
+ "movaz\t%0, za.d[%w1, 0, vgx<vector_count>]"
+)
+
+(define_insn "*aarch64_sme_readz<mode>_plus"
+ [(set (match_operand:SVE_DIx24 0 "aligned_register_operand" "=Uw<vector_count>")
+ (unspec:SVE_DIx24
+ [(reg:SVE_DIx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (plus:SI (match_operand:SI 1 "register_operand" "Uci")
+ (match_operand:SI 2 "const_0_to_7_operand"))
+ (const_int 0)]
+ UNSPEC_SME_READZ))
+ (set (reg:SVE_DIx24 ZA_REGNUM)
+ (unspec:SVE_DIx24
+ [(reg:SVE_DIx24 ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (plus:SI (match_dup 1)
+ (match_dup 2))
+ (const_int 1)]
+ UNSPEC_SME_READZ))]
+ "TARGET_STREAMING_SME2p1"
+ "movaz\t%0, za.d[%w1, %2, vgx<vector_count>]"
+)
+
(define_insn "@aarch64_sme_<optab><mode><mode>"
[(set (reg:SVE_FULLx24 ZA_REGNUM)
(unspec:SVE_FULLx24
;; - ZERO
;; -------------------------------------------------------------------------
-(define_c_enum "unspec" [UNSPEC_SME_ZERO])
+(define_c_enum "unspec" [UNSPEC_SME_ZERO UNSPEC_SME_ZERO_SLICES])
(define_insn "aarch64_sme_zero_za"
[(set (reg:VNx16QI ZA_REGNUM)
}
)
+(define_insn "@aarch64_sme_zero_za_slices<mode>"
+ [(set (reg:VNx16QI ZA_REGNUM)
+ (unspec:VNx16QI
+ [(reg:VNx16QI ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (scratch:SME_ZA_SDIx24)
+ (match_operand:SI 0 "register_operand" "Uci")]
+ UNSPEC_SME_ZERO_SLICES))]
+ "TARGET_STREAMING_SME2p1"
+ "zero\tza.d[%w0, 0, vgx<vector_count>]"
+)
+
+(define_insn "*aarch64_sme_zero_za_slices<mode>_plus"
+ [(set (reg:VNx16QI ZA_REGNUM)
+ (unspec:VNx16QI
+ [(reg:VNx16QI ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (scratch:SME_ZA_SDIx24)
+ (plus:SI (match_operand:SI 0 "register_operand" "Uci")
+ (match_operand:SI 1 "const_0_to_7_operand"))]
+ UNSPEC_SME_ZERO_SLICES))]
+ "TARGET_STREAMING_SME2p1"
+ "zero\tza.d[%w0, %1, vgx<vector_count>]"
+)
+
+(define_insn "@aarch64_sme_zero_za_slices<mode>"
+ [(set (reg:VNx16QI ZA_REGNUM)
+ (unspec:VNx16QI
+ [(reg:VNx16QI ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (scratch:SME_ZA_BHIx124)
+ (match_operand:SI 0 "register_operand" "Uci")]
+ UNSPEC_SME_ZERO_SLICES))]
+ "TARGET_STREAMING_SME2p1"
+ "zero\tza.d[%w0, 0:<za32_last_offset><vg_modifier>]"
+)
+
+(define_insn "*aarch64_sme_zero_za_slices<mode>_plus"
+ [(set (reg:VNx16QI ZA_REGNUM)
+ (unspec:VNx16QI
+ [(reg:VNx16QI ZA_REGNUM)
+ (reg:DI SME_STATE_REGNUM)
+ (scratch:SME_ZA_BHIx124)
+ (plus:SI (match_operand:SI 0 "register_operand" "Uci")
+ (match_operand:SI 1 "const_<za32_offset_range>_operand"))]
+ UNSPEC_SME_ZERO_SLICES))]
+ "TARGET_STREAMING_SME2p1"
+ {
+ operands[2] = GEN_INT (INTVAL (operands[1]) + <za32_last_offset>);
+ return "zero\tza.d[%w0, %1:%2<vg_modifier>]";
+ }
+)
+
(define_insn "aarch64_sme_zero_zt0"
[(set (reg:V8DI ZT0_REGNUM)
(const_int 0))
};
SHAPE (inherent_za)
+/* void svfoo_t0(uint64_t). */
+struct inherent_za_slice_def : public nonoverloaded_base
+{
+ void
+ build (function_builder &b, const function_group_info &group) const override
+ {
+ build_all (b, "_,su32", group, MODE_none);
+ }
+};
+SHAPE (inherent_za_slice)
+
/* void svfoo_zt(uint64_t)
where the argument must be zero. */
extern const function_shape *const inherent;
extern const function_shape *const inherent_b;
extern const function_shape *const inherent_za;
+ extern const function_shape *const inherent_za_slice;
extern const function_shape *const inherent_zt;
extern const function_shape *const inherent_mask_za;
extern const function_shape *const ldr_zt;
unsigned int m_bits;
};
-class svread_za_impl : public function_base
+template<insn_code (*CODE) (machine_mode)>
+class svread_za_slice_base : public function_base
{
public:
- unsigned int
- call_properties (const function_instance &) const override
- {
- return CP_READ_ZA;
- }
-
rtx
expand (function_expander &e) const override
{
machine_mode mode = e.vectors_per_tuple () == 4 ? VNx8DImode : VNx4DImode;
- rtx res = e.use_exact_insn (code_for_aarch64_sme_read (mode));
+ rtx res = e.use_exact_insn (CODE (mode));
return aarch64_sve_reinterpret (e.result_mode (), res);
}
};
+using svread_za_impl = add_call_properties
+ <svread_za_slice_base<code_for_aarch64_sme_read>, CP_READ_ZA>;
+
using svread_za_tile_impl = add_call_properties<read_write_za_base,
CP_READ_ZA>;
+using svreadz_za_impl = add_call_properties
+ <svread_za_slice_base<code_for_aarch64_sme_readz>, CP_READ_ZA | CP_WRITE_ZA>;
+
+using svreadz_za_tile_impl = add_call_properties<read_write_za_base,
+ CP_READ_ZA | CP_WRITE_ZA>;
+
class svst1_za_impl : public store_za_base
{
public:
}
};
+/* Return the mode iterator value that is used to represent a zeroing
+ of the ZA vectors described by GROUP. */
+static machine_mode
+zero_slices_mode (group_suffix_index group)
+{
+ switch (group)
+ {
+ case GROUP_vg1x2:
+ return VNx8SImode;
+ case GROUP_vg1x4:
+ return VNx16SImode;
+
+ case GROUP_vg2x1:
+ return VNx8HImode;
+ case GROUP_vg2x2:
+ return VNx16HImode;
+ case GROUP_vg2x4:
+ return VNx32HImode;
+
+ case GROUP_vg4x1:
+ return VNx16QImode;
+ case GROUP_vg4x2:
+ return VNx32QImode;
+ case GROUP_vg4x4:
+ return VNx64QImode;
+
+ default:
+ gcc_unreachable ();
+ }
+}
+
class svzero_za_impl : public write_za<function_base>
{
public:
rtx
- expand (function_expander &) const override
+ expand (function_expander &e) const override
{
+ if (e.args.length () == 1)
+ {
+ auto mode = zero_slices_mode (e.group_suffix_id);
+ return e.use_exact_insn (code_for_aarch64_sme_zero_za_slices (mode));
+ }
emit_insn (gen_aarch64_sme_zero_za (gen_int_mode (0xff, SImode)));
return const0_rtx;
}
FUNCTION (svread_za, svread_za_impl,)
FUNCTION (svread_hor_za, svread_za_tile_impl, (UNSPEC_SME_READ_HOR))
FUNCTION (svread_ver_za, svread_za_tile_impl, (UNSPEC_SME_READ_VER))
+FUNCTION (svreadz_za, svreadz_za_impl,)
+FUNCTION (svreadz_hor_za, svreadz_za_tile_impl, (UNSPEC_SME_READZ_HOR))
+FUNCTION (svreadz_ver_za, svreadz_za_tile_impl, (UNSPEC_SME_READZ_VER))
FUNCTION (svst1_hor_za, svst1_za_impl, (UNSPEC_SME_ST1_HOR))
FUNCTION (svst1_ver_za, svst1_za_impl, (UNSPEC_SME_ST1_VER))
FUNCTION (svstr_za, svstr_za_impl, )
DEF_SME_ZA_FUNCTION_GS (svsub, unary_za_slice, za_h_bfloat, vg1x24, none)
#undef REQUIRED_EXTENSIONS
+#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME2p1)
+DEF_SME_ZA_FUNCTION_GS (svreadz, read_za_slice, za_bhsd_data, vg1x24, none)
+DEF_SME_ZA_FUNCTION (svreadz_hor, read_za, za_all_data, none)
+DEF_SME_ZA_FUNCTION_GS (svreadz_hor, read_za, za_bhsd_data, vg24, none)
+DEF_SME_ZA_FUNCTION (svreadz_ver, read_za, za_all_data, none)
+DEF_SME_ZA_FUNCTION_GS (svreadz_ver, read_za, za_bhsd_data, vg24, none)
+DEF_SME_ZA_FUNCTION_GS (svzero, inherent_za_slice, d_za, vg1x24, none)
+DEF_SME_ZA_FUNCTION_GS (svzero, inherent_za_slice, d_za, vg2, none)
+DEF_SME_ZA_FUNCTION_GS (svzero, inherent_za_slice, d_za, vg4, none)
+#undef REQUIRED_EXTENSIONS
+
#undef DEF_SME_ZA_FUNCTION
#undef DEF_SME_ZA_FUNCTION_GS
#undef DEF_SME_FUNCTION
extern const function_base *const svread_za;
extern const function_base *const svread_hor_za;
extern const function_base *const svread_ver_za;
+ extern const function_base *const svreadz_za;
+ extern const function_base *const svreadz_hor_za;
+ extern const function_base *const svreadz_ver_za;
extern const function_base *const svst1_hor_za;
extern const function_base *const svst1_ver_za;
extern const function_base *const svstr_za;
/* Same with streaming mode enabled. */
#define TARGET_STREAMING_SME2 (TARGET_STREAMING && TARGET_SME2)
+#define TARGET_STREAMING_SME2p1 (TARGET_STREAMING && AARCH64_HAVE_ISA (SME2p1))
+
#define TARGET_SME_B16B16 AARCH64_HAVE_ISA (SME_B16B16)
/* ARMv8.3-A features. */
UNSPEC_SME_READ
UNSPEC_SME_READ_HOR
UNSPEC_SME_READ_VER
+ UNSPEC_SME_READZ
+ UNSPEC_SME_READZ_HOR
+ UNSPEC_SME_READZ_VER
UNSPEC_SME_SDOT
UNSPEC_SME_SVDOT
UNSPEC_SME_SMLA
(define_int_iterator SME_LD1 [UNSPEC_SME_LD1_HOR UNSPEC_SME_LD1_VER])
(define_int_iterator SME_READ_HV [UNSPEC_SME_READ_HOR UNSPEC_SME_READ_VER])
+(define_int_iterator SME_READZ_HV [UNSPEC_SME_READZ_HOR UNSPEC_SME_READZ_VER])
(define_int_iterator SME_ST1 [UNSPEC_SME_ST1_HOR UNSPEC_SME_ST1_VER])
(define_int_iterator SME_WRITE_HV [UNSPEC_SME_WRITE_HOR UNSPEC_SME_WRITE_VER])
(UNSPEC_SME_LD1_VER "ld1_ver")
(UNSPEC_SME_READ_HOR "read_hor")
(UNSPEC_SME_READ_VER "read_ver")
+ (UNSPEC_SME_READZ_HOR "readz_hor")
+ (UNSPEC_SME_READZ_VER "readz_ver")
(UNSPEC_SME_SDOT "sdot")
(UNSPEC_SME_SVDOT "svdot")
(UNSPEC_SME_SMLA "smla")
(UNSPEC_SME_LD1_VER "v")
(UNSPEC_SME_READ_HOR "h")
(UNSPEC_SME_READ_VER "v")
+ (UNSPEC_SME_READZ_HOR "h")
+ (UNSPEC_SME_READZ_VER "v")
(UNSPEC_SME_ST1_HOR "h")
(UNSPEC_SME_ST1_VER "v")
(UNSPEC_SME_WRITE_HOR "h")
@item sme-f16f16
Enable the FEAT_SME_F16F16 extension to SME. This also enables SME2
instructions.
+@item sme2p1
+Enable the Scalable Matrix Extension version 2.1. This also enables SME2
+instructions.
@item lse128
Enable the LSE128 128-bit atomic instructions extension. This also
enables LSE instructions.
#error Foo
#endif
+#pragma GCC target "+nothing+sme2p1"
+#ifndef __ARM_FEATURE_SME
+#error Foo
+#endif
+#ifndef __ARM_FEATURE_SME2
+#error Foo
+#endif
+#ifndef __ARM_FEATURE_SME2p1
+#error Foo
+#endif
+
#pragma GCC target "branch-protection=standard"
#ifndef __ARM_FEATURE_BTI_DEFAULT
#error Foo
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za128_s8_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_0_0, svint8_t,
+ z0 = svreadz_hor_za128_s8 (0, 0),
+ z0 = svreadz_hor_za128_s8 (0, 0))
+
+/*
+** readz_za128_s8_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_0_1, svint8_t,
+ z0 = svreadz_hor_za128_s8 (0, 1),
+ z0 = svreadz_hor_za128_s8 (0, 1))
+
+/*
+** readz_za128_s8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_0_w0, svint8_t,
+ z0 = svreadz_hor_za128_s8 (0, w0),
+ z0 = svreadz_hor_za128_s8 (0, w0))
+
+/*
+** readz_za128_s8_0_w0p1:
+** add (w1[2-5]), w0, #?1
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_0_w0p1, svint8_t,
+ z0 = svreadz_hor_za128_s8 (0, w0 + 1),
+ z0 = svreadz_hor_za128_s8 (0, w0 + 1))
+
+/*
+** readz_za128_s8_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_0_w0m1, svint8_t,
+ z0 = svreadz_hor_za128_s8 (0, w0 - 1),
+ z0 = svreadz_hor_za128_s8 (0, w0 - 1))
+
+/*
+** readz_za128_s8_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za1h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_1_w0, svint8_t,
+ z0 = svreadz_hor_za128_s8 (1, w0),
+ z0 = svreadz_hor_za128_s8 (1, w0))
+
+/*
+** readz_za128_s8_15_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za15h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s8_15_w0, svint8_t,
+ z0 = svreadz_hor_za128_s8 (15, w0),
+ z0 = svreadz_hor_za128_s8 (15, w0))
+
+/*
+** readz_za128_u8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_u8_0_w0, svuint8_t,
+ z0 = svreadz_hor_za128_u8 (0, w0),
+ z0 = svreadz_hor_za128_u8 (0, w0))
+
+/*
+** readz_za128_s16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s16_0_w0, svint16_t,
+ z0 = svreadz_hor_za128_s16 (0, w0),
+ z0 = svreadz_hor_za128_s16 (0, w0))
+
+/*
+** readz_za128_u16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_u16_0_w0, svuint16_t,
+ z0 = svreadz_hor_za128_u16 (0, w0),
+ z0 = svreadz_hor_za128_u16 (0, w0))
+
+/*
+** readz_za128_f16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_f16_0_w0, svfloat16_t,
+ z0 = svreadz_hor_za128_f16 (0, w0),
+ z0 = svreadz_hor_za128_f16 (0, w0))
+
+/*
+** readz_za128_bf16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_bf16_0_w0, svbfloat16_t,
+ z0 = svreadz_hor_za128_bf16 (0, w0),
+ z0 = svreadz_hor_za128_bf16 (0, w0))
+
+/*
+** readz_za128_s32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s32_0_w0, svint32_t,
+ z0 = svreadz_hor_za128_s32 (0, w0),
+ z0 = svreadz_hor_za128_s32 (0, w0))
+
+/*
+** readz_za128_u32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_u32_0_w0, svuint32_t,
+ z0 = svreadz_hor_za128_u32 (0, w0),
+ z0 = svreadz_hor_za128_u32 (0, w0))
+
+/*
+** readz_za128_f32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_f32_0_w0, svfloat32_t,
+ z0 = svreadz_hor_za128_f32 (0, w0),
+ z0 = svreadz_hor_za128_f32 (0, w0))
+
+/*
+** readz_za128_s64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_s64_0_w0, svint64_t,
+ z0 = svreadz_hor_za128_s64 (0, w0),
+ z0 = svreadz_hor_za128_s64 (0, w0))
+
+/*
+** readz_za128_u64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_u64_0_w0, svuint64_t,
+ z0 = svreadz_hor_za128_u64 (0, w0),
+ z0 = svreadz_hor_za128_u64 (0, w0))
+
+/*
+** readz_za128_f64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.q, za0h\.q\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za128_f64_0_w0, svfloat64_t,
+ z0 = svreadz_hor_za128_f64 (0, w0),
+ z0 = svreadz_hor_za128_f64 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_0, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, 0),
+ z0 = svreadz_hor_za16_s16 (0, 0))
+
+/*
+** readz_za16_s16_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_1, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, 1),
+ z0 = svreadz_hor_za16_s16 (0, 1))
+
+/*
+** readz_za16_s16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, w0),
+ z0 = svreadz_hor_za16_s16 (0, w0))
+
+/*
+** readz_za16_s16_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p1, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, w0 + 1),
+ z0 = svreadz_hor_za16_s16 (0, w0 + 1))
+
+/*
+** readz_za16_s16_0_w0p7:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 7\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p7, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, w0 + 7),
+ z0 = svreadz_hor_za16_s16 (0, w0 + 7))
+
+/*
+** readz_za16_s16_0_w0p8:
+** add (w1[2-5]), w0, #?8
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p8, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, w0 + 8),
+ z0 = svreadz_hor_za16_s16 (0, w0 + 8))
+
+/*
+** readz_za16_s16_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0m1, svint16_t,
+ z0 = svreadz_hor_za16_s16 (0, w0 - 1),
+ z0 = svreadz_hor_za16_s16 (0, w0 - 1))
+
+/*
+** readz_za16_s16_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za1h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_1_w0, svint16_t,
+ z0 = svreadz_hor_za16_s16 (1, w0),
+ z0 = svreadz_hor_za16_s16 (1, w0))
+
+/*
+** readz_za16_s16_1_w0p7:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za1h\.h\[\1, 7\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_1_w0p7, svint16_t,
+ z0 = svreadz_hor_za16_s16 (1, w0 + 7),
+ z0 = svreadz_hor_za16_s16 (1, w0 + 7))
+
+/*
+** readz_za16_u16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_u16_0_w0, svuint16_t,
+ z0 = svreadz_hor_za16_u16 (0, w0),
+ z0 = svreadz_hor_za16_u16 (0, w0))
+
+/*
+** readz_za16_f16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_f16_0_w0, svfloat16_t,
+ z0 = svreadz_hor_za16_f16 (0, w0),
+ z0 = svreadz_hor_za16_f16 (0, w0))
+
+/*
+** readz_za16_bf16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0h\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_bf16_0_w0, svbfloat16_t,
+ z0 = svreadz_hor_za16_bf16 (0, w0),
+ z0 = svreadz_hor_za16_bf16 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.h - z1\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_0, svint16x2_t,
+ z0 = svreadz_hor_za16_s16_vg2 (0, 0),
+ z0 = svreadz_hor_za16_s16_vg2 (0, 0))
+
+/*
+** readz_za16_u16_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.h - z5\.h}, za1h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_1_1, svuint16x2_t,
+ z4 = svreadz_hor_za16_u16_vg2 (1, 1),
+ z4 = svreadz_hor_za16_u16_vg2 (1, 1))
+
+/*
+** readz_za16_f16_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.h - z29\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z28_0_w11, svfloat16x2_t,
+ z28 = svreadz_hor_za16_f16_vg2 (0, w11),
+ z28 = svreadz_hor_za16_f16_vg2 (0, w11))
+
+/*
+** readz_za16_bf16_z0_1_w12:
+** movaz {z0\.h - z1\.h}, za1h\.h\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z0_1_w12, svbfloat16x2_t,
+ z0 = svreadz_hor_za16_bf16_vg2 (1, w12),
+ z0 = svreadz_hor_za16_bf16_vg2 (1, w12))
+
+/*
+** readz_za16_u16_z18_0_w15:
+** movaz {z18\.h - z19\.h}, za0h\.h\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_0_w15, svuint16x2_t,
+ z18 = svreadz_hor_za16_u16_vg2 (0, w15),
+ z18 = svreadz_hor_za16_u16_vg2 (0, w15))
+
+/*
+** readz_za16_s16_z23_1_w12p6:
+** movaz {[^\n]+}, za1h\.h\[w12, 6:7\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z23_1_w12p6, svint16x2_t,
+ z23 = svreadz_hor_za16_s16_vg2 (1, w12 + 6),
+ z23 = svreadz_hor_za16_s16_vg2 (1, w12 + 6))
+
+/*
+** readz_za16_f16_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.h - z5\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z4_0_w12p1, svfloat16x2_t,
+ z4 = svreadz_hor_za16_f16_vg2 (0, w12 + 1),
+ z4 = svreadz_hor_za16_f16_vg2 (0, w12 + 1))
+
+/*
+** readz_za16_s16_z28_1_w12p2:
+** movaz {z28\.h - z29\.h}, za1h\.h\[w12, 2:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z28_1_w12p2, svint16x2_t,
+ z28 = svreadz_hor_za16_s16_vg2 (1, w12 + 2),
+ z28 = svreadz_hor_za16_s16_vg2 (1, w12 + 2))
+
+/*
+** readz_za16_u16_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.h - z1\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z0_0_w15p3, svuint16x2_t,
+ z0 = svreadz_hor_za16_u16_vg2 (0, w15 + 3),
+ z0 = svreadz_hor_za16_u16_vg2 (0, w15 + 3))
+
+/*
+** readz_za16_bf16_z4_1_w15p4:
+** movaz {z4\.h - z5\.h}, za1h\.h\[w15, 4:5\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z4_1_w15p4, svbfloat16x2_t,
+ z4 = svreadz_hor_za16_bf16_vg2 (1, w15 + 4),
+ z4 = svreadz_hor_za16_bf16_vg2 (1, w15 + 4))
+
+/*
+** readz_za16_u16_z28_0_w12p7:
+** add (w[0-9]+), w12, #?7
+** movaz {z28\.h - z29\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_0_w12p7, svuint16x2_t,
+ z28 = svreadz_hor_za16_u16_vg2 (0, w12 + 7),
+ z28 = svreadz_hor_za16_u16_vg2 (0, w12 + 7))
+
+/*
+** readz_za16_s16_z0_1_w15p8:
+** add (w[0-9]+), w15, #?8
+** movaz {z0\.h - z1\.h}, za1h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_1_w15p8, svint16x2_t,
+ z0 = svreadz_hor_za16_s16_vg2 (1, w15 + 8),
+ z0 = svreadz_hor_za16_s16_vg2 (1, w15 + 8))
+
+/*
+** readz_za16_u16_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.h - z5\.h}, za0h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_0_w12m1, svuint16x2_t,
+ z4 = svreadz_hor_za16_u16_vg2 (0, w12 - 1),
+ z4 = svreadz_hor_za16_u16_vg2 (0, w12 - 1))
+
+/*
+** readz_za16_u16_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.h - z19\.h}, za1h\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_1_w16, svuint16x2_t,
+ z18 = svreadz_hor_za16_u16_vg2 (1, w16),
+ z18 = svreadz_hor_za16_u16_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.h - z3\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_0, svint16x4_t,
+ z0 = svreadz_hor_za16_s16_vg4 (0, 0),
+ z0 = svreadz_hor_za16_s16_vg4 (0, 0))
+
+/*
+** readz_za16_u16_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.h - z7\.h}, za1h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_1_1, svuint16x4_t,
+ z4 = svreadz_hor_za16_u16_vg4 (1, 1),
+ z4 = svreadz_hor_za16_u16_vg4 (1, 1))
+
+/*
+** readz_za16_f16_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.h - z31\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z28_0_w11, svfloat16x4_t,
+ z28 = svreadz_hor_za16_f16_vg4 (0, w11),
+ z28 = svreadz_hor_za16_f16_vg4 (0, w11))
+
+/*
+** readz_za16_s16_z0_1_w12:
+** movaz {z0\.h - z3\.h}, za1h\.h\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_1_w12, svint16x4_t,
+ z0 = svreadz_hor_za16_s16_vg4 (1, w12),
+ z0 = svreadz_hor_za16_s16_vg4 (1, w12))
+
+/*
+** readz_za16_u16_z18_0_w15:
+** movaz {[^\n]+}, za0h\.h\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_0_w15, svuint16x4_t,
+ z18 = svreadz_hor_za16_u16_vg4 (0, w15),
+ z18 = svreadz_hor_za16_u16_vg4 (0, w15))
+
+/*
+** readz_za16_bf16_z23_1_w12p4:
+** movaz {[^\n]+}, za1h\.h\[w12, 4:7\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z23_1_w12p4, svbfloat16x4_t,
+ z23 = svreadz_hor_za16_bf16_vg4 (1, w12 + 4),
+ z23 = svreadz_hor_za16_bf16_vg4 (1, w12 + 4))
+
+/*
+** readz_za16_u16_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.h - z7\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_0_w12p1, svuint16x4_t,
+ z4 = svreadz_hor_za16_u16_vg4 (0, w12 + 1),
+ z4 = svreadz_hor_za16_u16_vg4 (0, w12 + 1))
+
+/*
+** readz_za16_s16_z28_1_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.h - z31\.h}, za1h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z28_1_w12p2, svint16x4_t,
+ z28 = svreadz_hor_za16_s16_vg4 (1, w12 + 2),
+ z28 = svreadz_hor_za16_s16_vg4 (1, w12 + 2))
+
+/*
+** readz_za16_f16_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.h - z3\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z0_0_w15p3, svfloat16x4_t,
+ z0 = svreadz_hor_za16_f16_vg4 (0, w15 + 3),
+ z0 = svreadz_hor_za16_f16_vg4 (0, w15 + 3))
+
+/*
+** readz_za16_u16_z28_1_w12p6:
+** add (w[0-9]+), w12, #?6
+** movaz {z28\.h - z31\.h}, za1h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_1_w12p6, svuint16x4_t,
+ z28 = svreadz_hor_za16_u16_vg4 (1, w12 + 6),
+ z28 = svreadz_hor_za16_u16_vg4 (1, w12 + 6))
+
+/*
+** readz_za16_s16_z0_0_w15p8:
+** add (w[0-9]+), w15, #?8
+** movaz {z0\.h - z3\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_w15p8, svint16x4_t,
+ z0 = svreadz_hor_za16_s16_vg4 (0, w15 + 8),
+ z0 = svreadz_hor_za16_s16_vg4 (0, w15 + 8))
+
+/*
+** readz_za16_bf16_z4_1_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.h - z7\.h}, za1h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z4_1_w12m1, svbfloat16x4_t,
+ z4 = svreadz_hor_za16_bf16_vg4 (1, w12 - 1),
+ z4 = svreadz_hor_za16_bf16_vg4 (1, w12 - 1))
+
+/*
+** readz_za16_u16_z28_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.h - z31\.h}, za0h\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_0_w16, svuint16x4_t,
+ z28 = svreadz_hor_za16_u16_vg4 (0, w16),
+ z28 = svreadz_hor_za16_u16_vg4 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_0, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, 0),
+ z0 = svreadz_hor_za32_s32 (0, 0))
+
+/*
+** readz_za32_s32_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_1, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, 1),
+ z0 = svreadz_hor_za32_s32 (0, 1))
+
+/*
+** readz_za32_s32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, w0),
+ z0 = svreadz_hor_za32_s32 (0, w0))
+
+/*
+** readz_za32_s32_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0h\.s\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p1, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, w0 + 1),
+ z0 = svreadz_hor_za32_s32 (0, w0 + 1))
+
+/*
+** readz_za32_s32_0_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0h\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p3, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, w0 + 3),
+ z0 = svreadz_hor_za32_s32 (0, w0 + 3))
+
+/*
+** readz_za32_s32_0_w0p4:
+** add (w1[2-5]), w0, #?4
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p4, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, w0 + 4),
+ z0 = svreadz_hor_za32_s32 (0, w0 + 4))
+
+/*
+** readz_za32_s32_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0m1, svint32_t,
+ z0 = svreadz_hor_za32_s32 (0, w0 - 1),
+ z0 = svreadz_hor_za32_s32 (0, w0 - 1))
+
+/*
+** readz_za32_s32_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za1h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_1_w0, svint32_t,
+ z0 = svreadz_hor_za32_s32 (1, w0),
+ z0 = svreadz_hor_za32_s32 (1, w0))
+
+/*
+** readz_za32_s32_1_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za1h\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_1_w0p3, svint32_t,
+ z0 = svreadz_hor_za32_s32 (1, w0 + 3),
+ z0 = svreadz_hor_za32_s32 (1, w0 + 3))
+
+/*
+** readz_za32_s32_3_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za3h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_3_w0, svint32_t,
+ z0 = svreadz_hor_za32_s32 (3, w0),
+ z0 = svreadz_hor_za32_s32 (3, w0))
+
+/*
+** readz_za32_s32_3_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za3h\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_3_w0p3, svint32_t,
+ z0 = svreadz_hor_za32_s32 (3, w0 + 3),
+ z0 = svreadz_hor_za32_s32 (3, w0 + 3))
+
+/*
+** readz_za32_u32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_u32_0_w0, svuint32_t,
+ z0 = svreadz_hor_za32_u32 (0, w0),
+ z0 = svreadz_hor_za32_u32 (0, w0))
+
+/*
+** readz_za32_f32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0h\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_f32_0_w0, svfloat32_t,
+ z0 = svreadz_hor_za32_f32 (0, w0),
+ z0 = svreadz_hor_za32_f32 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.s - z1\.s}, za0h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_0_0, svint32x2_t,
+ z0 = svreadz_hor_za32_s32_vg2 (0, 0),
+ z0 = svreadz_hor_za32_s32_vg2 (0, 0))
+
+/*
+** readz_za32_u32_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.s - z5\.s}, za1h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_1_1, svuint32x2_t,
+ z4 = svreadz_hor_za32_u32_vg2 (1, 1),
+ z4 = svreadz_hor_za32_u32_vg2 (1, 1))
+
+/*
+** readz_za32_f32_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.s - z29\.s}, za2h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z28_2_w11, svfloat32x2_t,
+ z28 = svreadz_hor_za32_f32_vg2 (2, w11),
+ z28 = svreadz_hor_za32_f32_vg2 (2, w11))
+
+/*
+** readz_za32_f32_z0_3_w12:
+** movaz {z0\.s - z1\.s}, za3h\.s\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z0_3_w12, svfloat32x2_t,
+ z0 = svreadz_hor_za32_f32_vg2 (3, w12),
+ z0 = svreadz_hor_za32_f32_vg2 (3, w12))
+
+/*
+** readz_za32_u32_z18_0_w15:
+** movaz {z18\.s - z19\.s}, za0h\.s\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_0_w15, svuint32x2_t,
+ z18 = svreadz_hor_za32_u32_vg2 (0, w15),
+ z18 = svreadz_hor_za32_u32_vg2 (0, w15))
+
+/*
+** readz_za32_s32_z23_1_w12p2:
+** movaz {[^\n]+}, za1h\.s\[w12, 2:3\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z23_1_w12p2, svint32x2_t,
+ z23 = svreadz_hor_za32_s32_vg2 (1, w12 + 2),
+ z23 = svreadz_hor_za32_s32_vg2 (1, w12 + 2))
+
+/*
+** readz_za32_f32_z4_2_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.s - z5\.s}, za2h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z4_2_w12p1, svfloat32x2_t,
+ z4 = svreadz_hor_za32_f32_vg2 (2, w12 + 1),
+ z4 = svreadz_hor_za32_f32_vg2 (2, w12 + 1))
+
+/*
+** readz_za32_u32_z0_3_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.s - z1\.s}, za3h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z0_3_w15p3, svuint32x2_t,
+ z0 = svreadz_hor_za32_u32_vg2 (3, w15 + 3),
+ z0 = svreadz_hor_za32_u32_vg2 (3, w15 + 3))
+
+/*
+** readz_za32_s32_z0_1_w15p4:
+** add (w[0-9]+), w15, #?4
+** movaz {z0\.s - z1\.s}, za1h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_1_w15p4, svint32x2_t,
+ z0 = svreadz_hor_za32_s32_vg2 (1, w15 + 4),
+ z0 = svreadz_hor_za32_s32_vg2 (1, w15 + 4))
+
+/*
+** readz_za32_u32_z4_3_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.s - z5\.s}, za3h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_3_w12m1, svuint32x2_t,
+ z4 = svreadz_hor_za32_u32_vg2 (3, w12 - 1),
+ z4 = svreadz_hor_za32_u32_vg2 (3, w12 - 1))
+
+/*
+** readz_za32_u32_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.s - z19\.s}, za1h\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_1_w16, svuint32x2_t,
+ z18 = svreadz_hor_za32_u32_vg2 (1, w16),
+ z18 = svreadz_hor_za32_u32_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.s - z3\.s}, za0h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_0_0, svint32x4_t,
+ z0 = svreadz_hor_za32_s32_vg4 (0, 0),
+ z0 = svreadz_hor_za32_s32_vg4 (0, 0))
+
+/*
+** readz_za32_u32_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.s - z7\.s}, za1h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_1_1, svuint32x4_t,
+ z4 = svreadz_hor_za32_u32_vg4 (1, 1),
+ z4 = svreadz_hor_za32_u32_vg4 (1, 1))
+
+/*
+** readz_za32_f32_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.s - z31\.s}, za2h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z28_2_w11, svfloat32x4_t,
+ z28 = svreadz_hor_za32_f32_vg4 (2, w11),
+ z28 = svreadz_hor_za32_f32_vg4 (2, w11))
+
+/*
+** readz_za32_s32_z0_3_w12:
+** movaz {z0\.s - z3\.s}, za3h\.s\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_3_w12, svint32x4_t,
+ z0 = svreadz_hor_za32_s32_vg4 (3, w12),
+ z0 = svreadz_hor_za32_s32_vg4 (3, w12))
+
+/*
+** readz_za32_u32_z18_0_w15:
+** movaz {[^\n]+}, za0h\.s\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_0_w15, svuint32x4_t,
+ z18 = svreadz_hor_za32_u32_vg4 (0, w15),
+ z18 = svreadz_hor_za32_u32_vg4 (0, w15))
+
+/*
+** readz_za32_f32_z23_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {[^\n]+}, za1h\.s\[\1, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z23_1_w12p4, svfloat32x4_t,
+ z23 = svreadz_hor_za32_f32_vg4 (1, w12 + 4),
+ z23 = svreadz_hor_za32_f32_vg4 (1, w12 + 4))
+
+/*
+** readz_za32_u32_z4_2_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.s - z7\.s}, za2h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_2_w12p1, svuint32x4_t,
+ z4 = svreadz_hor_za32_u32_vg4 (2, w12 + 1),
+ z4 = svreadz_hor_za32_u32_vg4 (2, w12 + 1))
+
+/*
+** readz_za32_s32_z28_3_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.s - z31\.s}, za3h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z28_3_w12p2, svint32x4_t,
+ z28 = svreadz_hor_za32_s32_vg4 (3, w12 + 2),
+ z28 = svreadz_hor_za32_s32_vg4 (3, w12 + 2))
+
+/*
+** readz_za32_f32_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.s - z3\.s}, za0h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z0_0_w15p3, svfloat32x4_t,
+ z0 = svreadz_hor_za32_f32_vg4 (0, w15 + 3),
+ z0 = svreadz_hor_za32_f32_vg4 (0, w15 + 3))
+
+/*
+** readz_za32_u32_z28_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {z28\.s - z31\.s}, za1h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z28_1_w12p4, svuint32x4_t,
+ z28 = svreadz_hor_za32_u32_vg4 (1, w12 + 4),
+ z28 = svreadz_hor_za32_u32_vg4 (1, w12 + 4))
+
+/*
+** readz_za32_f32_z4_2_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.s - z7\.s}, za2h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z4_2_w12m1, svfloat32x4_t,
+ z4 = svreadz_hor_za32_f32_vg4 (2, w12 - 1),
+ z4 = svreadz_hor_za32_f32_vg4 (2, w12 - 1))
+
+/*
+** readz_za32_u32_z28_3_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.s - z31\.s}, za3h\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z28_3_w16, svuint32x4_t,
+ z28 = svreadz_hor_za32_u32_vg4 (3, w16),
+ z28 = svreadz_hor_za32_u32_vg4 (3, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_0, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, 0),
+ z0 = svreadz_hor_za64_s64 (0, 0))
+
+/*
+** readz_za64_s64_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_1, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, 1),
+ z0 = svreadz_hor_za64_s64 (0, 1))
+
+/*
+** readz_za64_s64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, w0),
+ z0 = svreadz_hor_za64_s64 (0, w0))
+
+/*
+** readz_za64_s64_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0h\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0p1, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, w0 + 1),
+ z0 = svreadz_hor_za64_s64 (0, w0 + 1))
+
+/*
+** readz_za64_s64_0_w0p2:
+** add (w1[2-5]), w0, #?2
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0p2, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, w0 + 2),
+ z0 = svreadz_hor_za64_s64 (0, w0 + 2))
+
+/*
+** readz_za64_s64_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0m1, svint64_t,
+ z0 = svreadz_hor_za64_s64 (0, w0 - 1),
+ z0 = svreadz_hor_za64_s64 (0, w0 - 1))
+
+/*
+** readz_za64_s64_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za1h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_1_w0, svint64_t,
+ z0 = svreadz_hor_za64_s64 (1, w0),
+ z0 = svreadz_hor_za64_s64 (1, w0))
+
+/*
+** readz_za64_s64_1_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za1h\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_1_w0p1, svint64_t,
+ z0 = svreadz_hor_za64_s64 (1, w0 + 1),
+ z0 = svreadz_hor_za64_s64 (1, w0 + 1))
+
+/*
+** readz_za64_s64_7_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za7h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_7_w0, svint64_t,
+ z0 = svreadz_hor_za64_s64 (7, w0),
+ z0 = svreadz_hor_za64_s64 (7, w0))
+
+/*
+** readz_za64_s64_7_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za7h\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_7_w0p1, svint64_t,
+ z0 = svreadz_hor_za64_s64 (7, w0 + 1),
+ z0 = svreadz_hor_za64_s64 (7, w0 + 1))
+
+/*
+** readz_za64_u64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_u64_0_w0, svuint64_t,
+ z0 = svreadz_hor_za64_u64 (0, w0),
+ z0 = svreadz_hor_za64_u64 (0, w0))
+
+/*
+** readz_za64_f64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0h\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_f64_0_w0, svfloat64_t,
+ z0 = svreadz_hor_za64_f64 (0, w0),
+ z0 = svreadz_hor_za64_f64 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.d - z1\.d}, za0h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_0_0, svint64x2_t,
+ z0 = svreadz_hor_za64_s64_vg2 (0, 0),
+ z0 = svreadz_hor_za64_s64_vg2 (0, 0))
+
+/*
+** readz_za64_u64_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.d - z5\.d}, za1h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_1_1, svuint64x2_t,
+ z4 = svreadz_hor_za64_u64_vg2 (1, 1),
+ z4 = svreadz_hor_za64_u64_vg2 (1, 1))
+
+/*
+** readz_za64_f64_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.d - z29\.d}, za2h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z28_2_w11, svfloat64x2_t,
+ z28 = svreadz_hor_za64_f64_vg2 (2, w11),
+ z28 = svreadz_hor_za64_f64_vg2 (2, w11))
+
+/*
+** readz_za64_f64_z0_3_w12:
+** movaz {z0\.d - z1\.d}, za3h\.d\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z0_3_w12, svfloat64x2_t,
+ z0 = svreadz_hor_za64_f64_vg2 (3, w12),
+ z0 = svreadz_hor_za64_f64_vg2 (3, w12))
+
+/*
+** readz_za64_u64_z18_4_w15:
+** movaz {z18\.d - z19\.d}, za4h\.d\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_4_w15, svuint64x2_t,
+ z18 = svreadz_hor_za64_u64_vg2 (4, w15),
+ z18 = svreadz_hor_za64_u64_vg2 (4, w15))
+
+/*
+** readz_za64_s64_z23_5_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {[^\n]+}, za5h\.d\[\1, 0:1\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z23_5_w12p2, svint64x2_t,
+ z23 = svreadz_hor_za64_s64_vg2 (5, w12 + 2),
+ z23 = svreadz_hor_za64_s64_vg2 (5, w12 + 2))
+
+/*
+** readz_za64_f64_z4_6_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.d - z5\.d}, za6h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z4_6_w12p1, svfloat64x2_t,
+ z4 = svreadz_hor_za64_f64_vg2 (6, w12 + 1),
+ z4 = svreadz_hor_za64_f64_vg2 (6, w12 + 1))
+
+/*
+** readz_za64_u64_z0_7_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.d - z1\.d}, za7h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z0_7_w15p3, svuint64x2_t,
+ z0 = svreadz_hor_za64_u64_vg2 (7, w15 + 3),
+ z0 = svreadz_hor_za64_u64_vg2 (7, w15 + 3))
+
+/*
+** readz_za64_s64_z0_1_w15p4:
+** add (w[0-9]+), w15, #?4
+** movaz {z0\.d - z1\.d}, za1h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_1_w15p4, svint64x2_t,
+ z0 = svreadz_hor_za64_s64_vg2 (1, w15 + 4),
+ z0 = svreadz_hor_za64_s64_vg2 (1, w15 + 4))
+
+/*
+** readz_za64_u64_z4_3_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.d - z5\.d}, za3h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_3_w12m1, svuint64x2_t,
+ z4 = svreadz_hor_za64_u64_vg2 (3, w12 - 1),
+ z4 = svreadz_hor_za64_u64_vg2 (3, w12 - 1))
+
+/*
+** readz_za64_u64_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.d - z19\.d}, za1h\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_1_w16, svuint64x2_t,
+ z18 = svreadz_hor_za64_u64_vg2 (1, w16),
+ z18 = svreadz_hor_za64_u64_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.d - z3\.d}, za0h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_0_0, svint64x4_t,
+ z0 = svreadz_hor_za64_s64_vg4 (0, 0),
+ z0 = svreadz_hor_za64_s64_vg4 (0, 0))
+
+/*
+** readz_za64_u64_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.d - z7\.d}, za1h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_1_1, svuint64x4_t,
+ z4 = svreadz_hor_za64_u64_vg4 (1, 1),
+ z4 = svreadz_hor_za64_u64_vg4 (1, 1))
+
+/*
+** readz_za64_f64_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.d - z31\.d}, za2h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z28_2_w11, svfloat64x4_t,
+ z28 = svreadz_hor_za64_f64_vg4 (2, w11),
+ z28 = svreadz_hor_za64_f64_vg4 (2, w11))
+
+/*
+** readz_za64_s64_z0_3_w12:
+** movaz {z0\.d - z3\.d}, za3h\.d\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_3_w12, svint64x4_t,
+ z0 = svreadz_hor_za64_s64_vg4 (3, w12),
+ z0 = svreadz_hor_za64_s64_vg4 (3, w12))
+
+/*
+** readz_za64_u64_z18_4_w15:
+** movaz {[^\n]+}, za4h\.d\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_4_w15, svuint64x4_t,
+ z18 = svreadz_hor_za64_u64_vg4 (4, w15),
+ z18 = svreadz_hor_za64_u64_vg4 (4, w15))
+
+/*
+** readz_za64_f64_z23_5_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {[^\n]+}, za5h\.d\[\1, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z23_5_w12p4, svfloat64x4_t,
+ z23 = svreadz_hor_za64_f64_vg4 (5, w12 + 4),
+ z23 = svreadz_hor_za64_f64_vg4 (5, w12 + 4))
+
+/*
+** readz_za64_u64_z4_6_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.d - z7\.d}, za6h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_6_w12p1, svuint64x4_t,
+ z4 = svreadz_hor_za64_u64_vg4 (6, w12 + 1),
+ z4 = svreadz_hor_za64_u64_vg4 (6, w12 + 1))
+
+/*
+** readz_za64_s64_z28_7_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.d - z31\.d}, za7h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z28_7_w12p2, svint64x4_t,
+ z28 = svreadz_hor_za64_s64_vg4 (7, w12 + 2),
+ z28 = svreadz_hor_za64_s64_vg4 (7, w12 + 2))
+
+/*
+** readz_za64_f64_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.d - z3\.d}, za0h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z0_0_w15p3, svfloat64x4_t,
+ z0 = svreadz_hor_za64_f64_vg4 (0, w15 + 3),
+ z0 = svreadz_hor_za64_f64_vg4 (0, w15 + 3))
+
+/*
+** readz_za64_u64_z28_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {z28\.d - z31\.d}, za1h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z28_1_w12p4, svuint64x4_t,
+ z28 = svreadz_hor_za64_u64_vg4 (1, w12 + 4),
+ z28 = svreadz_hor_za64_u64_vg4 (1, w12 + 4))
+
+/*
+** readz_za64_f64_z4_2_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.d - z7\.d}, za2h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z4_2_w12m1, svfloat64x4_t,
+ z4 = svreadz_hor_za64_f64_vg4 (2, w12 - 1),
+ z4 = svreadz_hor_za64_f64_vg4 (2, w12 - 1))
+
+/*
+** readz_za64_u64_z28_3_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.d - z31\.d}, za3h\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z28_3_w16, svuint64x4_t,
+ z28 = svreadz_hor_za64_u64_vg4 (3, w16),
+ z28 = svreadz_hor_za64_u64_vg4 (3, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_0, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, 0),
+ z0 = svreadz_hor_za8_s8 (0, 0))
+
+/*
+** readz_za8_s8_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_1, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, 1),
+ z0 = svreadz_hor_za8_s8 (0, 1))
+
+/*
+** readz_za8_s8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, w0),
+ z0 = svreadz_hor_za8_s8 (0, w0))
+
+/*
+** readz_za8_s8_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0h\.b\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p1, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, w0 + 1),
+ z0 = svreadz_hor_za8_s8 (0, w0 + 1))
+
+/*
+** readz_za8_s8_0_w0p15:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0h\.b\[\1, 15\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p15, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, w0 + 15),
+ z0 = svreadz_hor_za8_s8 (0, w0 + 15))
+
+/*
+** readz_za8_s8_0_w0p16:
+** add (w1[2-5]), w0, #?16
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p16, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, w0 + 16),
+ z0 = svreadz_hor_za8_s8 (0, w0 + 16))
+
+/*
+** readz_za8_s8_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0m1, svint8_t,
+ z0 = svreadz_hor_za8_s8 (0, w0 - 1),
+ z0 = svreadz_hor_za8_s8 (0, w0 - 1))
+
+/*
+** readz_za8_u8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0h\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_u8_0_w0, svuint8_t,
+ z0 = svreadz_hor_za8_u8 (0, w0),
+ z0 = svreadz_hor_za8_u8 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.b - z1\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_0, svint8x2_t,
+ z0 = svreadz_hor_za8_s8_vg2 (0, 0),
+ z0 = svreadz_hor_za8_s8_vg2 (0, 0))
+
+/*
+** readz_za8_u8_z4_0_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.b - z5\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_1, svuint8x2_t,
+ z4 = svreadz_hor_za8_u8_vg2 (0, 1),
+ z4 = svreadz_hor_za8_u8_vg2 (0, 1))
+
+/*
+** readz_za8_s8_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.b - z29\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w11, svint8x2_t,
+ z28 = svreadz_hor_za8_s8_vg2 (0, w11),
+ z28 = svreadz_hor_za8_s8_vg2 (0, w11))
+
+/*
+** readz_za8_s8_z0_0_w12:
+** movaz {z0\.b - z1\.b}, za0h\.b\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w12, svint8x2_t,
+ z0 = svreadz_hor_za8_s8_vg2 (0, w12),
+ z0 = svreadz_hor_za8_s8_vg2 (0, w12))
+
+/*
+** readz_za8_u8_z18_0_w15:
+** movaz {z18\.b - z19\.b}, za0h\.b\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w15, svuint8x2_t,
+ z18 = svreadz_hor_za8_u8_vg2 (0, w15),
+ z18 = svreadz_hor_za8_u8_vg2 (0, w15))
+
+/*
+** readz_za8_s8_z23_0_w12p14:
+** movaz {[^\n]+}, za0h\.b\[w12, 14:15\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z23_0_w12p14, svint8x2_t,
+ z23 = svreadz_hor_za8_s8_vg2 (0, w12 + 14),
+ z23 = svreadz_hor_za8_s8_vg2 (0, w12 + 14))
+
+/*
+** readz_za8_u8_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.b - z5\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12p1, svuint8x2_t,
+ z4 = svreadz_hor_za8_u8_vg2 (0, w12 + 1),
+ z4 = svreadz_hor_za8_u8_vg2 (0, w12 + 1))
+
+/*
+** readz_za8_s8_z28_0_w12p2:
+** movaz {z28\.b - z29\.b}, za0h\.b\[w12, 2:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w12p2, svint8x2_t,
+ z28 = svreadz_hor_za8_s8_vg2 (0, w12 + 2),
+ z28 = svreadz_hor_za8_s8_vg2 (0, w12 + 2))
+
+/*
+** readz_za8_u8_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.b - z1\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w15p3, svuint8x2_t,
+ z0 = svreadz_hor_za8_u8_vg2 (0, w15 + 3),
+ z0 = svreadz_hor_za8_u8_vg2 (0, w15 + 3))
+
+/*
+** readz_za8_u8_z4_0_w15p12:
+** movaz {z4\.b - z5\.b}, za0h\.b\[w15, 12:13\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w15p12, svuint8x2_t,
+ z4 = svreadz_hor_za8_u8_vg2 (0, w15 + 12),
+ z4 = svreadz_hor_za8_u8_vg2 (0, w15 + 12))
+
+/*
+** readz_za8_u8_z28_0_w12p15:
+** add (w[0-9]+), w12, #?15
+** movaz {z28\.b - z29\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w12p15, svuint8x2_t,
+ z28 = svreadz_hor_za8_u8_vg2 (0, w12 + 15),
+ z28 = svreadz_hor_za8_u8_vg2 (0, w12 + 15))
+
+/*
+** readz_za8_s8_z0_0_w15p16:
+** add (w[0-9]+), w15, #?16
+** movaz {z0\.b - z1\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w15p16, svint8x2_t,
+ z0 = svreadz_hor_za8_s8_vg2 (0, w15 + 16),
+ z0 = svreadz_hor_za8_s8_vg2 (0, w15 + 16))
+
+/*
+** readz_za8_u8_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.b - z5\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12m1, svuint8x2_t,
+ z4 = svreadz_hor_za8_u8_vg2 (0, w12 - 1),
+ z4 = svreadz_hor_za8_u8_vg2 (0, w12 - 1))
+
+/*
+** readz_za8_u8_z18_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.b - z19\.b}, za0h\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w16, svuint8x2_t,
+ z18 = svreadz_hor_za8_u8_vg2 (0, w16),
+ z18 = svreadz_hor_za8_u8_vg2 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.b - z3\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_0, svint8x4_t,
+ z0 = svreadz_hor_za8_s8_vg4 (0, 0),
+ z0 = svreadz_hor_za8_s8_vg4 (0, 0))
+
+/*
+** readz_za8_u8_z4_0_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.b - z7\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_1, svuint8x4_t,
+ z4 = svreadz_hor_za8_u8_vg4 (0, 1),
+ z4 = svreadz_hor_za8_u8_vg4 (0, 1))
+
+/*
+** readz_za8_s8_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.b - z31\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w11, svint8x4_t,
+ z28 = svreadz_hor_za8_s8_vg4 (0, w11),
+ z28 = svreadz_hor_za8_s8_vg4 (0, w11))
+
+/*
+** readz_za8_s8_z0_0_w12:
+** movaz {z0\.b - z3\.b}, za0h\.b\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w12, svint8x4_t,
+ z0 = svreadz_hor_za8_s8_vg4 (0, w12),
+ z0 = svreadz_hor_za8_s8_vg4 (0, w12))
+
+/*
+** readz_za8_u8_z18_0_w15:
+** movaz {[^\n]+}, za0h\.b\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w15, svuint8x4_t,
+ z18 = svreadz_hor_za8_u8_vg4 (0, w15),
+ z18 = svreadz_hor_za8_u8_vg4 (0, w15))
+
+/*
+** readz_za8_s8_z23_0_w12p12:
+** movaz {[^\n]+}, za0h\.b\[w12, 12:15\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z23_0_w12p12, svint8x4_t,
+ z23 = svreadz_hor_za8_s8_vg4 (0, w12 + 12),
+ z23 = svreadz_hor_za8_s8_vg4 (0, w12 + 12))
+
+/*
+** readz_za8_u8_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.b - z7\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12p1, svuint8x4_t,
+ z4 = svreadz_hor_za8_u8_vg4 (0, w12 + 1),
+ z4 = svreadz_hor_za8_u8_vg4 (0, w12 + 1))
+
+/*
+** readz_za8_s8_z28_0_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.b - z31\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w12p2, svint8x4_t,
+ z28 = svreadz_hor_za8_s8_vg4 (0, w12 + 2),
+ z28 = svreadz_hor_za8_s8_vg4 (0, w12 + 2))
+
+/*
+** readz_za8_u8_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.b - z3\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w15p3, svuint8x4_t,
+ z0 = svreadz_hor_za8_u8_vg4 (0, w15 + 3),
+ z0 = svreadz_hor_za8_u8_vg4 (0, w15 + 3))
+
+/*
+** readz_za8_u8_z0_0_w12p4:
+** movaz {z0\.b - z3\.b}, za0h\.b\[w12, 4:7\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w12p4, svuint8x4_t,
+ z0 = svreadz_hor_za8_u8_vg4 (0, w12 + 4),
+ z0 = svreadz_hor_za8_u8_vg4 (0, w12 + 4))
+
+/*
+** readz_za8_u8_z4_0_w15p12:
+** movaz {z4\.b - z7\.b}, za0h\.b\[w15, 12:15\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w15p12, svuint8x4_t,
+ z4 = svreadz_hor_za8_u8_vg4 (0, w15 + 12),
+ z4 = svreadz_hor_za8_u8_vg4 (0, w15 + 12))
+
+/*
+** readz_za8_u8_z28_0_w12p14:
+** add (w[0-9]+), w12, #?14
+** movaz {z28\.b - z31\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w12p14, svuint8x4_t,
+ z28 = svreadz_hor_za8_u8_vg4 (0, w12 + 14),
+ z28 = svreadz_hor_za8_u8_vg4 (0, w12 + 14))
+
+/*
+** readz_za8_s8_z0_0_w15p16:
+** add (w[0-9]+), w15, #?16
+** movaz {z0\.b - z3\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w15p16, svint8x4_t,
+ z0 = svreadz_hor_za8_s8_vg4 (0, w15 + 16),
+ z0 = svreadz_hor_za8_s8_vg4 (0, w15 + 16))
+
+/*
+** readz_za8_u8_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.b - z7\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12m1, svuint8x4_t,
+ z4 = svreadz_hor_za8_u8_vg4 (0, w12 - 1),
+ z4 = svreadz_hor_za8_u8_vg4 (0, w12 - 1))
+
+/*
+** readz_za8_u8_z28_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.b - z31\.b}, za0h\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w16, svuint8x4_t,
+ z28 = svreadz_hor_za8_u8_vg4 (0, w16),
+ z28 = svreadz_hor_za8_u8_vg4 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_0, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, 0),
+ z0 = svreadz_ver_za16_s16 (0, 0))
+
+/*
+** readz_za16_s16_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_1, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, 1),
+ z0 = svreadz_ver_za16_s16 (0, 1))
+
+/*
+** readz_za16_s16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, w0),
+ z0 = svreadz_ver_za16_s16 (0, w0))
+
+/*
+** readz_za16_s16_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p1, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, w0 + 1),
+ z0 = svreadz_ver_za16_s16 (0, w0 + 1))
+
+/*
+** readz_za16_s16_0_w0p7:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 7\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p7, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, w0 + 7),
+ z0 = svreadz_ver_za16_s16 (0, w0 + 7))
+
+/*
+** readz_za16_s16_0_w0p8:
+** add (w1[2-5]), w0, #?8
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0p8, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, w0 + 8),
+ z0 = svreadz_ver_za16_s16 (0, w0 + 8))
+
+/*
+** readz_za16_s16_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_0_w0m1, svint16_t,
+ z0 = svreadz_ver_za16_s16 (0, w0 - 1),
+ z0 = svreadz_ver_za16_s16 (0, w0 - 1))
+
+/*
+** readz_za16_s16_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za1v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_1_w0, svint16_t,
+ z0 = svreadz_ver_za16_s16 (1, w0),
+ z0 = svreadz_ver_za16_s16 (1, w0))
+
+/*
+** readz_za16_s16_1_w0p7:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za1v\.h\[\1, 7\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_s16_1_w0p7, svint16_t,
+ z0 = svreadz_ver_za16_s16 (1, w0 + 7),
+ z0 = svreadz_ver_za16_s16 (1, w0 + 7))
+
+/*
+** readz_za16_u16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_u16_0_w0, svuint16_t,
+ z0 = svreadz_ver_za16_u16 (0, w0),
+ z0 = svreadz_ver_za16_u16 (0, w0))
+
+/*
+** readz_za16_f16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_f16_0_w0, svfloat16_t,
+ z0 = svreadz_ver_za16_f16 (0, w0),
+ z0 = svreadz_ver_za16_f16 (0, w0))
+
+/*
+** readz_za16_bf16_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.h, za0v\.h\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za16_bf16_0_w0, svbfloat16_t,
+ z0 = svreadz_ver_za16_bf16 (0, w0),
+ z0 = svreadz_ver_za16_bf16 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.h - z1\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_0, svint16x2_t,
+ z0 = svreadz_ver_za16_s16_vg2 (0, 0),
+ z0 = svreadz_ver_za16_s16_vg2 (0, 0))
+
+/*
+** readz_za16_u16_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.h - z5\.h}, za1v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_1_1, svuint16x2_t,
+ z4 = svreadz_ver_za16_u16_vg2 (1, 1),
+ z4 = svreadz_ver_za16_u16_vg2 (1, 1))
+
+/*
+** readz_za16_f16_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.h - z29\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z28_0_w11, svfloat16x2_t,
+ z28 = svreadz_ver_za16_f16_vg2 (0, w11),
+ z28 = svreadz_ver_za16_f16_vg2 (0, w11))
+
+/*
+** readz_za16_bf16_z0_1_w12:
+** movaz {z0\.h - z1\.h}, za1v\.h\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z0_1_w12, svbfloat16x2_t,
+ z0 = svreadz_ver_za16_bf16_vg2 (1, w12),
+ z0 = svreadz_ver_za16_bf16_vg2 (1, w12))
+
+/*
+** readz_za16_u16_z18_0_w15:
+** movaz {z18\.h - z19\.h}, za0v\.h\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_0_w15, svuint16x2_t,
+ z18 = svreadz_ver_za16_u16_vg2 (0, w15),
+ z18 = svreadz_ver_za16_u16_vg2 (0, w15))
+
+/*
+** readz_za16_s16_z23_1_w12p6:
+** movaz {[^\n]+}, za1v\.h\[w12, 6:7\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z23_1_w12p6, svint16x2_t,
+ z23 = svreadz_ver_za16_s16_vg2 (1, w12 + 6),
+ z23 = svreadz_ver_za16_s16_vg2 (1, w12 + 6))
+
+/*
+** readz_za16_f16_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.h - z5\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z4_0_w12p1, svfloat16x2_t,
+ z4 = svreadz_ver_za16_f16_vg2 (0, w12 + 1),
+ z4 = svreadz_ver_za16_f16_vg2 (0, w12 + 1))
+
+/*
+** readz_za16_s16_z28_1_w12p2:
+** movaz {z28\.h - z29\.h}, za1v\.h\[w12, 2:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z28_1_w12p2, svint16x2_t,
+ z28 = svreadz_ver_za16_s16_vg2 (1, w12 + 2),
+ z28 = svreadz_ver_za16_s16_vg2 (1, w12 + 2))
+
+/*
+** readz_za16_u16_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.h - z1\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z0_0_w15p3, svuint16x2_t,
+ z0 = svreadz_ver_za16_u16_vg2 (0, w15 + 3),
+ z0 = svreadz_ver_za16_u16_vg2 (0, w15 + 3))
+
+/*
+** readz_za16_bf16_z4_1_w15p4:
+** movaz {z4\.h - z5\.h}, za1v\.h\[w15, 4:5\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z4_1_w15p4, svbfloat16x2_t,
+ z4 = svreadz_ver_za16_bf16_vg2 (1, w15 + 4),
+ z4 = svreadz_ver_za16_bf16_vg2 (1, w15 + 4))
+
+/*
+** readz_za16_u16_z28_0_w12p7:
+** add (w[0-9]+), w12, #?7
+** movaz {z28\.h - z29\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_0_w12p7, svuint16x2_t,
+ z28 = svreadz_ver_za16_u16_vg2 (0, w12 + 7),
+ z28 = svreadz_ver_za16_u16_vg2 (0, w12 + 7))
+
+/*
+** readz_za16_s16_z0_1_w15p8:
+** add (w[0-9]+), w15, #?8
+** movaz {z0\.h - z1\.h}, za1v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_1_w15p8, svint16x2_t,
+ z0 = svreadz_ver_za16_s16_vg2 (1, w15 + 8),
+ z0 = svreadz_ver_za16_s16_vg2 (1, w15 + 8))
+
+/*
+** readz_za16_u16_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.h - z5\.h}, za0v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_0_w12m1, svuint16x2_t,
+ z4 = svreadz_ver_za16_u16_vg2 (0, w12 - 1),
+ z4 = svreadz_ver_za16_u16_vg2 (0, w12 - 1))
+
+/*
+** readz_za16_u16_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.h - z19\.h}, za1v\.h\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_1_w16, svuint16x2_t,
+ z18 = svreadz_ver_za16_u16_vg2 (1, w16),
+ z18 = svreadz_ver_za16_u16_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za16_s16_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.h - z3\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_0, svint16x4_t,
+ z0 = svreadz_ver_za16_s16_vg4 (0, 0),
+ z0 = svreadz_ver_za16_s16_vg4 (0, 0))
+
+/*
+** readz_za16_u16_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.h - z7\.h}, za1v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_1_1, svuint16x4_t,
+ z4 = svreadz_ver_za16_u16_vg4 (1, 1),
+ z4 = svreadz_ver_za16_u16_vg4 (1, 1))
+
+/*
+** readz_za16_f16_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.h - z31\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z28_0_w11, svfloat16x4_t,
+ z28 = svreadz_ver_za16_f16_vg4 (0, w11),
+ z28 = svreadz_ver_za16_f16_vg4 (0, w11))
+
+/*
+** readz_za16_s16_z0_1_w12:
+** movaz {z0\.h - z3\.h}, za1v\.h\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_1_w12, svint16x4_t,
+ z0 = svreadz_ver_za16_s16_vg4 (1, w12),
+ z0 = svreadz_ver_za16_s16_vg4 (1, w12))
+
+/*
+** readz_za16_u16_z18_0_w15:
+** movaz {[^\n]+}, za0v\.h\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z18_0_w15, svuint16x4_t,
+ z18 = svreadz_ver_za16_u16_vg4 (0, w15),
+ z18 = svreadz_ver_za16_u16_vg4 (0, w15))
+
+/*
+** readz_za16_bf16_z23_1_w12p4:
+** movaz {[^\n]+}, za1v\.h\[w12, 4:7\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z23_1_w12p4, svbfloat16x4_t,
+ z23 = svreadz_ver_za16_bf16_vg4 (1, w12 + 4),
+ z23 = svreadz_ver_za16_bf16_vg4 (1, w12 + 4))
+
+/*
+** readz_za16_u16_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.h - z7\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z4_0_w12p1, svuint16x4_t,
+ z4 = svreadz_ver_za16_u16_vg4 (0, w12 + 1),
+ z4 = svreadz_ver_za16_u16_vg4 (0, w12 + 1))
+
+/*
+** readz_za16_s16_z28_1_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.h - z31\.h}, za1v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z28_1_w12p2, svint16x4_t,
+ z28 = svreadz_ver_za16_s16_vg4 (1, w12 + 2),
+ z28 = svreadz_ver_za16_s16_vg4 (1, w12 + 2))
+
+/*
+** readz_za16_f16_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.h - z3\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_f16_z0_0_w15p3, svfloat16x4_t,
+ z0 = svreadz_ver_za16_f16_vg4 (0, w15 + 3),
+ z0 = svreadz_ver_za16_f16_vg4 (0, w15 + 3))
+
+/*
+** readz_za16_u16_z28_1_w12p6:
+** add (w[0-9]+), w12, #?6
+** movaz {z28\.h - z31\.h}, za1v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_1_w12p6, svuint16x4_t,
+ z28 = svreadz_ver_za16_u16_vg4 (1, w12 + 6),
+ z28 = svreadz_ver_za16_u16_vg4 (1, w12 + 6))
+
+/*
+** readz_za16_s16_z0_0_w15p8:
+** add (w[0-9]+), w15, #?8
+** movaz {z0\.h - z3\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_s16_z0_0_w15p8, svint16x4_t,
+ z0 = svreadz_ver_za16_s16_vg4 (0, w15 + 8),
+ z0 = svreadz_ver_za16_s16_vg4 (0, w15 + 8))
+
+/*
+** readz_za16_bf16_z4_1_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.h - z7\.h}, za1v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_bf16_z4_1_w12m1, svbfloat16x4_t,
+ z4 = svreadz_ver_za16_bf16_vg4 (1, w12 - 1),
+ z4 = svreadz_ver_za16_bf16_vg4 (1, w12 - 1))
+
+/*
+** readz_za16_u16_z28_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.h - z31\.h}, za0v\.h\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za16_u16_z28_0_w16, svuint16x4_t,
+ z28 = svreadz_ver_za16_u16_vg4 (0, w16),
+ z28 = svreadz_ver_za16_u16_vg4 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_0, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, 0),
+ z0 = svreadz_ver_za32_s32 (0, 0))
+
+/*
+** readz_za32_s32_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_1, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, 1),
+ z0 = svreadz_ver_za32_s32 (0, 1))
+
+/*
+** readz_za32_s32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, w0),
+ z0 = svreadz_ver_za32_s32 (0, w0))
+
+/*
+** readz_za32_s32_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0v\.s\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p1, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, w0 + 1),
+ z0 = svreadz_ver_za32_s32 (0, w0 + 1))
+
+/*
+** readz_za32_s32_0_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0v\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p3, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, w0 + 3),
+ z0 = svreadz_ver_za32_s32 (0, w0 + 3))
+
+/*
+** readz_za32_s32_0_w0p4:
+** add (w1[2-5]), w0, #?4
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0p4, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, w0 + 4),
+ z0 = svreadz_ver_za32_s32 (0, w0 + 4))
+
+/*
+** readz_za32_s32_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_0_w0m1, svint32_t,
+ z0 = svreadz_ver_za32_s32 (0, w0 - 1),
+ z0 = svreadz_ver_za32_s32 (0, w0 - 1))
+
+/*
+** readz_za32_s32_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za1v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_1_w0, svint32_t,
+ z0 = svreadz_ver_za32_s32 (1, w0),
+ z0 = svreadz_ver_za32_s32 (1, w0))
+
+/*
+** readz_za32_s32_1_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za1v\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_1_w0p3, svint32_t,
+ z0 = svreadz_ver_za32_s32 (1, w0 + 3),
+ z0 = svreadz_ver_za32_s32 (1, w0 + 3))
+
+/*
+** readz_za32_s32_3_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za3v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_3_w0, svint32_t,
+ z0 = svreadz_ver_za32_s32 (3, w0),
+ z0 = svreadz_ver_za32_s32 (3, w0))
+
+/*
+** readz_za32_s32_3_w0p3:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za3v\.s\[\1, 3\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_s32_3_w0p3, svint32_t,
+ z0 = svreadz_ver_za32_s32 (3, w0 + 3),
+ z0 = svreadz_ver_za32_s32 (3, w0 + 3))
+
+/*
+** readz_za32_u32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_u32_0_w0, svuint32_t,
+ z0 = svreadz_ver_za32_u32 (0, w0),
+ z0 = svreadz_ver_za32_u32 (0, w0))
+
+/*
+** readz_za32_f32_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.s, za0v\.s\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za32_f32_0_w0, svfloat32_t,
+ z0 = svreadz_ver_za32_f32 (0, w0),
+ z0 = svreadz_ver_za32_f32 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.s - z1\.s}, za0v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_0_0, svint32x2_t,
+ z0 = svreadz_ver_za32_s32_vg2 (0, 0),
+ z0 = svreadz_ver_za32_s32_vg2 (0, 0))
+
+/*
+** readz_za32_u32_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.s - z5\.s}, za1v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_1_1, svuint32x2_t,
+ z4 = svreadz_ver_za32_u32_vg2 (1, 1),
+ z4 = svreadz_ver_za32_u32_vg2 (1, 1))
+
+/*
+** readz_za32_f32_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.s - z29\.s}, za2v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z28_2_w11, svfloat32x2_t,
+ z28 = svreadz_ver_za32_f32_vg2 (2, w11),
+ z28 = svreadz_ver_za32_f32_vg2 (2, w11))
+
+/*
+** readz_za32_f32_z0_3_w12:
+** movaz {z0\.s - z1\.s}, za3v\.s\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z0_3_w12, svfloat32x2_t,
+ z0 = svreadz_ver_za32_f32_vg2 (3, w12),
+ z0 = svreadz_ver_za32_f32_vg2 (3, w12))
+
+/*
+** readz_za32_u32_z18_0_w15:
+** movaz {z18\.s - z19\.s}, za0v\.s\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_0_w15, svuint32x2_t,
+ z18 = svreadz_ver_za32_u32_vg2 (0, w15),
+ z18 = svreadz_ver_za32_u32_vg2 (0, w15))
+
+/*
+** readz_za32_s32_z23_1_w12p2:
+** movaz {[^\n]+}, za1v\.s\[w12, 2:3\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z23_1_w12p2, svint32x2_t,
+ z23 = svreadz_ver_za32_s32_vg2 (1, w12 + 2),
+ z23 = svreadz_ver_za32_s32_vg2 (1, w12 + 2))
+
+/*
+** readz_za32_f32_z4_2_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.s - z5\.s}, za2v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z4_2_w12p1, svfloat32x2_t,
+ z4 = svreadz_ver_za32_f32_vg2 (2, w12 + 1),
+ z4 = svreadz_ver_za32_f32_vg2 (2, w12 + 1))
+
+/*
+** readz_za32_u32_z0_3_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.s - z1\.s}, za3v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z0_3_w15p3, svuint32x2_t,
+ z0 = svreadz_ver_za32_u32_vg2 (3, w15 + 3),
+ z0 = svreadz_ver_za32_u32_vg2 (3, w15 + 3))
+
+/*
+** readz_za32_s32_z0_1_w15p4:
+** add (w[0-9]+), w15, #?4
+** movaz {z0\.s - z1\.s}, za1v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_1_w15p4, svint32x2_t,
+ z0 = svreadz_ver_za32_s32_vg2 (1, w15 + 4),
+ z0 = svreadz_ver_za32_s32_vg2 (1, w15 + 4))
+
+/*
+** readz_za32_u32_z4_3_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.s - z5\.s}, za3v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_3_w12m1, svuint32x2_t,
+ z4 = svreadz_ver_za32_u32_vg2 (3, w12 - 1),
+ z4 = svreadz_ver_za32_u32_vg2 (3, w12 - 1))
+
+/*
+** readz_za32_u32_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.s - z19\.s}, za1v\.s\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_1_w16, svuint32x2_t,
+ z18 = svreadz_ver_za32_u32_vg2 (1, w16),
+ z18 = svreadz_ver_za32_u32_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za32_s32_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.s - z3\.s}, za0v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_0_0, svint32x4_t,
+ z0 = svreadz_ver_za32_s32_vg4 (0, 0),
+ z0 = svreadz_ver_za32_s32_vg4 (0, 0))
+
+/*
+** readz_za32_u32_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.s - z7\.s}, za1v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_1_1, svuint32x4_t,
+ z4 = svreadz_ver_za32_u32_vg4 (1, 1),
+ z4 = svreadz_ver_za32_u32_vg4 (1, 1))
+
+/*
+** readz_za32_f32_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.s - z31\.s}, za2v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z28_2_w11, svfloat32x4_t,
+ z28 = svreadz_ver_za32_f32_vg4 (2, w11),
+ z28 = svreadz_ver_za32_f32_vg4 (2, w11))
+
+/*
+** readz_za32_s32_z0_3_w12:
+** movaz {z0\.s - z3\.s}, za3v\.s\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z0_3_w12, svint32x4_t,
+ z0 = svreadz_ver_za32_s32_vg4 (3, w12),
+ z0 = svreadz_ver_za32_s32_vg4 (3, w12))
+
+/*
+** readz_za32_u32_z18_0_w15:
+** movaz {[^\n]+}, za0v\.s\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z18_0_w15, svuint32x4_t,
+ z18 = svreadz_ver_za32_u32_vg4 (0, w15),
+ z18 = svreadz_ver_za32_u32_vg4 (0, w15))
+
+/*
+** readz_za32_f32_z23_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {[^\n]+}, za1v\.s\[\1, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z23_1_w12p4, svfloat32x4_t,
+ z23 = svreadz_ver_za32_f32_vg4 (1, w12 + 4),
+ z23 = svreadz_ver_za32_f32_vg4 (1, w12 + 4))
+
+/*
+** readz_za32_u32_z4_2_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.s - z7\.s}, za2v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z4_2_w12p1, svuint32x4_t,
+ z4 = svreadz_ver_za32_u32_vg4 (2, w12 + 1),
+ z4 = svreadz_ver_za32_u32_vg4 (2, w12 + 1))
+
+/*
+** readz_za32_s32_z28_3_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.s - z31\.s}, za3v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_s32_z28_3_w12p2, svint32x4_t,
+ z28 = svreadz_ver_za32_s32_vg4 (3, w12 + 2),
+ z28 = svreadz_ver_za32_s32_vg4 (3, w12 + 2))
+
+/*
+** readz_za32_f32_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.s - z3\.s}, za0v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z0_0_w15p3, svfloat32x4_t,
+ z0 = svreadz_ver_za32_f32_vg4 (0, w15 + 3),
+ z0 = svreadz_ver_za32_f32_vg4 (0, w15 + 3))
+
+/*
+** readz_za32_u32_z28_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {z28\.s - z31\.s}, za1v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z28_1_w12p4, svuint32x4_t,
+ z28 = svreadz_ver_za32_u32_vg4 (1, w12 + 4),
+ z28 = svreadz_ver_za32_u32_vg4 (1, w12 + 4))
+
+/*
+** readz_za32_f32_z4_2_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.s - z7\.s}, za2v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_f32_z4_2_w12m1, svfloat32x4_t,
+ z4 = svreadz_ver_za32_f32_vg4 (2, w12 - 1),
+ z4 = svreadz_ver_za32_f32_vg4 (2, w12 - 1))
+
+/*
+** readz_za32_u32_z28_3_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.s - z31\.s}, za3v\.s\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za32_u32_z28_3_w16, svuint32x4_t,
+ z28 = svreadz_ver_za32_u32_vg4 (3, w16),
+ z28 = svreadz_ver_za32_u32_vg4 (3, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_0, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, 0),
+ z0 = svreadz_ver_za64_s64 (0, 0))
+
+/*
+** readz_za64_s64_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_1, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, 1),
+ z0 = svreadz_ver_za64_s64 (0, 1))
+
+/*
+** readz_za64_s64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, w0),
+ z0 = svreadz_ver_za64_s64 (0, w0))
+
+/*
+** readz_za64_s64_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0v\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0p1, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, w0 + 1),
+ z0 = svreadz_ver_za64_s64 (0, w0 + 1))
+
+/*
+** readz_za64_s64_0_w0p2:
+** add (w1[2-5]), w0, #?2
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0p2, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, w0 + 2),
+ z0 = svreadz_ver_za64_s64 (0, w0 + 2))
+
+/*
+** readz_za64_s64_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_0_w0m1, svint64_t,
+ z0 = svreadz_ver_za64_s64 (0, w0 - 1),
+ z0 = svreadz_ver_za64_s64 (0, w0 - 1))
+
+/*
+** readz_za64_s64_1_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za1v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_1_w0, svint64_t,
+ z0 = svreadz_ver_za64_s64 (1, w0),
+ z0 = svreadz_ver_za64_s64 (1, w0))
+
+/*
+** readz_za64_s64_1_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za1v\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_1_w0p1, svint64_t,
+ z0 = svreadz_ver_za64_s64 (1, w0 + 1),
+ z0 = svreadz_ver_za64_s64 (1, w0 + 1))
+
+/*
+** readz_za64_s64_7_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za7v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_7_w0, svint64_t,
+ z0 = svreadz_ver_za64_s64 (7, w0),
+ z0 = svreadz_ver_za64_s64 (7, w0))
+
+/*
+** readz_za64_s64_7_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za7v\.d\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_s64_7_w0p1, svint64_t,
+ z0 = svreadz_ver_za64_s64 (7, w0 + 1),
+ z0 = svreadz_ver_za64_s64 (7, w0 + 1))
+
+/*
+** readz_za64_u64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_u64_0_w0, svuint64_t,
+ z0 = svreadz_ver_za64_u64 (0, w0),
+ z0 = svreadz_ver_za64_u64 (0, w0))
+
+/*
+** readz_za64_f64_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.d, za0v\.d\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za64_f64_0_w0, svfloat64_t,
+ z0 = svreadz_ver_za64_f64 (0, w0),
+ z0 = svreadz_ver_za64_f64 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.d - z1\.d}, za0v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_0_0, svint64x2_t,
+ z0 = svreadz_ver_za64_s64_vg2 (0, 0),
+ z0 = svreadz_ver_za64_s64_vg2 (0, 0))
+
+/*
+** readz_za64_u64_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.d - z5\.d}, za1v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_1_1, svuint64x2_t,
+ z4 = svreadz_ver_za64_u64_vg2 (1, 1),
+ z4 = svreadz_ver_za64_u64_vg2 (1, 1))
+
+/*
+** readz_za64_f64_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.d - z29\.d}, za2v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z28_2_w11, svfloat64x2_t,
+ z28 = svreadz_ver_za64_f64_vg2 (2, w11),
+ z28 = svreadz_ver_za64_f64_vg2 (2, w11))
+
+/*
+** readz_za64_f64_z0_3_w12:
+** movaz {z0\.d - z1\.d}, za3v\.d\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z0_3_w12, svfloat64x2_t,
+ z0 = svreadz_ver_za64_f64_vg2 (3, w12),
+ z0 = svreadz_ver_za64_f64_vg2 (3, w12))
+
+/*
+** readz_za64_u64_z18_4_w15:
+** movaz {z18\.d - z19\.d}, za4v\.d\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_4_w15, svuint64x2_t,
+ z18 = svreadz_ver_za64_u64_vg2 (4, w15),
+ z18 = svreadz_ver_za64_u64_vg2 (4, w15))
+
+/*
+** readz_za64_s64_z23_5_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {[^\n]+}, za5v\.d\[\1, 0:1\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z23_5_w12p2, svint64x2_t,
+ z23 = svreadz_ver_za64_s64_vg2 (5, w12 + 2),
+ z23 = svreadz_ver_za64_s64_vg2 (5, w12 + 2))
+
+/*
+** readz_za64_f64_z4_6_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.d - z5\.d}, za6v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z4_6_w12p1, svfloat64x2_t,
+ z4 = svreadz_ver_za64_f64_vg2 (6, w12 + 1),
+ z4 = svreadz_ver_za64_f64_vg2 (6, w12 + 1))
+
+/*
+** readz_za64_u64_z0_7_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.d - z1\.d}, za7v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z0_7_w15p3, svuint64x2_t,
+ z0 = svreadz_ver_za64_u64_vg2 (7, w15 + 3),
+ z0 = svreadz_ver_za64_u64_vg2 (7, w15 + 3))
+
+/*
+** readz_za64_s64_z0_1_w15p4:
+** add (w[0-9]+), w15, #?4
+** movaz {z0\.d - z1\.d}, za1v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_1_w15p4, svint64x2_t,
+ z0 = svreadz_ver_za64_s64_vg2 (1, w15 + 4),
+ z0 = svreadz_ver_za64_s64_vg2 (1, w15 + 4))
+
+/*
+** readz_za64_u64_z4_3_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.d - z5\.d}, za3v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_3_w12m1, svuint64x2_t,
+ z4 = svreadz_ver_za64_u64_vg2 (3, w12 - 1),
+ z4 = svreadz_ver_za64_u64_vg2 (3, w12 - 1))
+
+/*
+** readz_za64_u64_z18_1_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.d - z19\.d}, za1v\.d\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_1_w16, svuint64x2_t,
+ z18 = svreadz_ver_za64_u64_vg2 (1, w16),
+ z18 = svreadz_ver_za64_u64_vg2 (1, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za64_s64_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.d - z3\.d}, za0v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_0_0, svint64x4_t,
+ z0 = svreadz_ver_za64_s64_vg4 (0, 0),
+ z0 = svreadz_ver_za64_s64_vg4 (0, 0))
+
+/*
+** readz_za64_u64_z4_1_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.d - z7\.d}, za1v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_1_1, svuint64x4_t,
+ z4 = svreadz_ver_za64_u64_vg4 (1, 1),
+ z4 = svreadz_ver_za64_u64_vg4 (1, 1))
+
+/*
+** readz_za64_f64_z28_2_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.d - z31\.d}, za2v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z28_2_w11, svfloat64x4_t,
+ z28 = svreadz_ver_za64_f64_vg4 (2, w11),
+ z28 = svreadz_ver_za64_f64_vg4 (2, w11))
+
+/*
+** readz_za64_s64_z0_3_w12:
+** movaz {z0\.d - z3\.d}, za3v\.d\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z0_3_w12, svint64x4_t,
+ z0 = svreadz_ver_za64_s64_vg4 (3, w12),
+ z0 = svreadz_ver_za64_s64_vg4 (3, w12))
+
+/*
+** readz_za64_u64_z18_4_w15:
+** movaz {[^\n]+}, za4v\.d\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z18_4_w15, svuint64x4_t,
+ z18 = svreadz_ver_za64_u64_vg4 (4, w15),
+ z18 = svreadz_ver_za64_u64_vg4 (4, w15))
+
+/*
+** readz_za64_f64_z23_5_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {[^\n]+}, za5v\.d\[\1, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z23_5_w12p4, svfloat64x4_t,
+ z23 = svreadz_ver_za64_f64_vg4 (5, w12 + 4),
+ z23 = svreadz_ver_za64_f64_vg4 (5, w12 + 4))
+
+/*
+** readz_za64_u64_z4_6_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.d - z7\.d}, za6v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z4_6_w12p1, svuint64x4_t,
+ z4 = svreadz_ver_za64_u64_vg4 (6, w12 + 1),
+ z4 = svreadz_ver_za64_u64_vg4 (6, w12 + 1))
+
+/*
+** readz_za64_s64_z28_7_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.d - z31\.d}, za7v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_s64_z28_7_w12p2, svint64x4_t,
+ z28 = svreadz_ver_za64_s64_vg4 (7, w12 + 2),
+ z28 = svreadz_ver_za64_s64_vg4 (7, w12 + 2))
+
+/*
+** readz_za64_f64_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.d - z3\.d}, za0v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z0_0_w15p3, svfloat64x4_t,
+ z0 = svreadz_ver_za64_f64_vg4 (0, w15 + 3),
+ z0 = svreadz_ver_za64_f64_vg4 (0, w15 + 3))
+
+/*
+** readz_za64_u64_z28_1_w12p4:
+** add (w[0-9]+), w12, #?4
+** movaz {z28\.d - z31\.d}, za1v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z28_1_w12p4, svuint64x4_t,
+ z28 = svreadz_ver_za64_u64_vg4 (1, w12 + 4),
+ z28 = svreadz_ver_za64_u64_vg4 (1, w12 + 4))
+
+/*
+** readz_za64_f64_z4_2_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.d - z7\.d}, za2v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_f64_z4_2_w12m1, svfloat64x4_t,
+ z4 = svreadz_ver_za64_f64_vg4 (2, w12 - 1),
+ z4 = svreadz_ver_za64_f64_vg4 (2, w12 - 1))
+
+/*
+** readz_za64_u64_z28_3_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.d - z31\.d}, za3v\.d\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za64_u64_z28_3_w16, svuint64x4_t,
+ z28 = svreadz_ver_za64_u64_vg4 (3, w16),
+ z28 = svreadz_ver_za64_u64_vg4 (3, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_0, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, 0),
+ z0 = svreadz_ver_za8_s8 (0, 0))
+
+/*
+** readz_za8_s8_0_1:
+** mov (w1[2-5]), #?1
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_1, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, 1),
+ z0 = svreadz_ver_za8_s8 (0, 1))
+
+/*
+** readz_za8_s8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, w0),
+ z0 = svreadz_ver_za8_s8 (0, w0))
+
+/*
+** readz_za8_s8_0_w0p1:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0v\.b\[\1, 1\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p1, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, w0 + 1),
+ z0 = svreadz_ver_za8_s8 (0, w0 + 1))
+
+/*
+** readz_za8_s8_0_w0p15:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0v\.b\[\1, 15\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p15, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, w0 + 15),
+ z0 = svreadz_ver_za8_s8 (0, w0 + 15))
+
+/*
+** readz_za8_s8_0_w0p16:
+** add (w1[2-5]), w0, #?16
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0p16, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, w0 + 16),
+ z0 = svreadz_ver_za8_s8 (0, w0 + 16))
+
+/*
+** readz_za8_s8_0_w0m1:
+** sub (w1[2-5]), w0, #?1
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_s8_0_w0m1, svint8_t,
+ z0 = svreadz_ver_za8_s8 (0, w0 - 1),
+ z0 = svreadz_ver_za8_s8 (0, w0 - 1))
+
+/*
+** readz_za8_u8_0_w0:
+** mov (w1[2-5]), w0
+** movaz z0\.b, za0v\.b\[\1, 0\]
+** ret
+*/
+TEST_READ_ZA (readz_za8_u8_0_w0, svuint8_t,
+ z0 = svreadz_ver_za8_u8 (0, w0),
+ z0 = svreadz_ver_za8_u8 (0, w0))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.b - z1\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_0, svint8x2_t,
+ z0 = svreadz_ver_za8_s8_vg2 (0, 0),
+ z0 = svreadz_ver_za8_s8_vg2 (0, 0))
+
+/*
+** readz_za8_u8_z4_0_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.b - z5\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_1, svuint8x2_t,
+ z4 = svreadz_ver_za8_u8_vg2 (0, 1),
+ z4 = svreadz_ver_za8_u8_vg2 (0, 1))
+
+/*
+** readz_za8_s8_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.b - z29\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w11, svint8x2_t,
+ z28 = svreadz_ver_za8_s8_vg2 (0, w11),
+ z28 = svreadz_ver_za8_s8_vg2 (0, w11))
+
+/*
+** readz_za8_s8_z0_0_w12:
+** movaz {z0\.b - z1\.b}, za0v\.b\[w12, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w12, svint8x2_t,
+ z0 = svreadz_ver_za8_s8_vg2 (0, w12),
+ z0 = svreadz_ver_za8_s8_vg2 (0, w12))
+
+/*
+** readz_za8_u8_z18_0_w15:
+** movaz {z18\.b - z19\.b}, za0v\.b\[w15, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w15, svuint8x2_t,
+ z18 = svreadz_ver_za8_u8_vg2 (0, w15),
+ z18 = svreadz_ver_za8_u8_vg2 (0, w15))
+
+/*
+** readz_za8_s8_z23_0_w12p14:
+** movaz {[^\n]+}, za0v\.b\[w12, 14:15\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z23_0_w12p14, svint8x2_t,
+ z23 = svreadz_ver_za8_s8_vg2 (0, w12 + 14),
+ z23 = svreadz_ver_za8_s8_vg2 (0, w12 + 14))
+
+/*
+** readz_za8_u8_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.b - z5\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12p1, svuint8x2_t,
+ z4 = svreadz_ver_za8_u8_vg2 (0, w12 + 1),
+ z4 = svreadz_ver_za8_u8_vg2 (0, w12 + 1))
+
+/*
+** readz_za8_s8_z28_0_w12p2:
+** movaz {z28\.b - z29\.b}, za0v\.b\[w12, 2:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w12p2, svint8x2_t,
+ z28 = svreadz_ver_za8_s8_vg2 (0, w12 + 2),
+ z28 = svreadz_ver_za8_s8_vg2 (0, w12 + 2))
+
+/*
+** readz_za8_u8_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.b - z1\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w15p3, svuint8x2_t,
+ z0 = svreadz_ver_za8_u8_vg2 (0, w15 + 3),
+ z0 = svreadz_ver_za8_u8_vg2 (0, w15 + 3))
+
+/*
+** readz_za8_u8_z4_0_w15p12:
+** movaz {z4\.b - z5\.b}, za0v\.b\[w15, 12:13\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w15p12, svuint8x2_t,
+ z4 = svreadz_ver_za8_u8_vg2 (0, w15 + 12),
+ z4 = svreadz_ver_za8_u8_vg2 (0, w15 + 12))
+
+/*
+** readz_za8_u8_z28_0_w12p15:
+** add (w[0-9]+), w12, #?15
+** movaz {z28\.b - z29\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w12p15, svuint8x2_t,
+ z28 = svreadz_ver_za8_u8_vg2 (0, w12 + 15),
+ z28 = svreadz_ver_za8_u8_vg2 (0, w12 + 15))
+
+/*
+** readz_za8_s8_z0_0_w15p16:
+** add (w[0-9]+), w15, #?16
+** movaz {z0\.b - z1\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w15p16, svint8x2_t,
+ z0 = svreadz_ver_za8_s8_vg2 (0, w15 + 16),
+ z0 = svreadz_ver_za8_s8_vg2 (0, w15 + 16))
+
+/*
+** readz_za8_u8_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.b - z5\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12m1, svuint8x2_t,
+ z4 = svreadz_ver_za8_u8_vg2 (0, w12 - 1),
+ z4 = svreadz_ver_za8_u8_vg2 (0, w12 - 1))
+
+/*
+** readz_za8_u8_z18_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z18\.b - z19\.b}, za0v\.b\[\1, 0:1\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w16, svuint8x2_t,
+ z18 = svreadz_ver_za8_u8_vg2 (0, w16),
+ z18 = svreadz_ver_za8_u8_vg2 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_za8_s8_z0_0_0:
+** mov (w1[2-5]), (?:wzr|#?0)
+** movaz {z0\.b - z3\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_0, svint8x4_t,
+ z0 = svreadz_ver_za8_s8_vg4 (0, 0),
+ z0 = svreadz_ver_za8_s8_vg4 (0, 0))
+
+/*
+** readz_za8_u8_z4_0_1:
+** mov (w1[2-5]), #?1
+** movaz {z4\.b - z7\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_1, svuint8x4_t,
+ z4 = svreadz_ver_za8_u8_vg4 (0, 1),
+ z4 = svreadz_ver_za8_u8_vg4 (0, 1))
+
+/*
+** readz_za8_s8_z28_0_w11:
+** mov (w1[2-5]), w11
+** movaz {z28\.b - z31\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w11, svint8x4_t,
+ z28 = svreadz_ver_za8_s8_vg4 (0, w11),
+ z28 = svreadz_ver_za8_s8_vg4 (0, w11))
+
+/*
+** readz_za8_s8_z0_0_w12:
+** movaz {z0\.b - z3\.b}, za0v\.b\[w12, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w12, svint8x4_t,
+ z0 = svreadz_ver_za8_s8_vg4 (0, w12),
+ z0 = svreadz_ver_za8_s8_vg4 (0, w12))
+
+/*
+** readz_za8_u8_z18_0_w15:
+** movaz {[^\n]+}, za0v\.b\[w15, 0:3\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z18_0_w15, svuint8x4_t,
+ z18 = svreadz_ver_za8_u8_vg4 (0, w15),
+ z18 = svreadz_ver_za8_u8_vg4 (0, w15))
+
+/*
+** readz_za8_s8_z23_0_w12p12:
+** movaz {[^\n]+}, za0v\.b\[w12, 12:15\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z23_0_w12p12, svint8x4_t,
+ z23 = svreadz_ver_za8_s8_vg4 (0, w12 + 12),
+ z23 = svreadz_ver_za8_s8_vg4 (0, w12 + 12))
+
+/*
+** readz_za8_u8_z4_0_w12p1:
+** add (w[0-9]+), w12, #?1
+** movaz {z4\.b - z7\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12p1, svuint8x4_t,
+ z4 = svreadz_ver_za8_u8_vg4 (0, w12 + 1),
+ z4 = svreadz_ver_za8_u8_vg4 (0, w12 + 1))
+
+/*
+** readz_za8_s8_z28_0_w12p2:
+** add (w[0-9]+), w12, #?2
+** movaz {z28\.b - z31\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z28_0_w12p2, svint8x4_t,
+ z28 = svreadz_ver_za8_s8_vg4 (0, w12 + 2),
+ z28 = svreadz_ver_za8_s8_vg4 (0, w12 + 2))
+
+/*
+** readz_za8_u8_z0_0_w15p3:
+** add (w[0-9]+), w15, #?3
+** movaz {z0\.b - z3\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w15p3, svuint8x4_t,
+ z0 = svreadz_ver_za8_u8_vg4 (0, w15 + 3),
+ z0 = svreadz_ver_za8_u8_vg4 (0, w15 + 3))
+
+/*
+** readz_za8_u8_z0_0_w12p4:
+** movaz {z0\.b - z3\.b}, za0v\.b\[w12, 4:7\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z0_0_w12p4, svuint8x4_t,
+ z0 = svreadz_ver_za8_u8_vg4 (0, w12 + 4),
+ z0 = svreadz_ver_za8_u8_vg4 (0, w12 + 4))
+
+/*
+** readz_za8_u8_z4_0_w15p12:
+** movaz {z4\.b - z7\.b}, za0v\.b\[w15, 12:15\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w15p12, svuint8x4_t,
+ z4 = svreadz_ver_za8_u8_vg4 (0, w15 + 12),
+ z4 = svreadz_ver_za8_u8_vg4 (0, w15 + 12))
+
+/*
+** readz_za8_u8_z28_0_w12p14:
+** add (w[0-9]+), w12, #?14
+** movaz {z28\.b - z31\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w12p14, svuint8x4_t,
+ z28 = svreadz_ver_za8_u8_vg4 (0, w12 + 14),
+ z28 = svreadz_ver_za8_u8_vg4 (0, w12 + 14))
+
+/*
+** readz_za8_s8_z0_0_w15p16:
+** add (w[0-9]+), w15, #?16
+** movaz {z0\.b - z3\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_s8_z0_0_w15p16, svint8x4_t,
+ z0 = svreadz_ver_za8_s8_vg4 (0, w15 + 16),
+ z0 = svreadz_ver_za8_s8_vg4 (0, w15 + 16))
+
+/*
+** readz_za8_u8_z4_0_w12m1:
+** sub (w[0-9]+), w12, #?1
+** movaz {z4\.b - z7\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z4_0_w12m1, svuint8x4_t,
+ z4 = svreadz_ver_za8_u8_vg4 (0, w12 - 1),
+ z4 = svreadz_ver_za8_u8_vg4 (0, w12 - 1))
+
+/*
+** readz_za8_u8_z28_0_w16:
+** mov (w1[2-5]), w16
+** movaz {z28\.b - z31\.b}, za0v\.b\[\1, 0:3\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_za8_u8_z28_0_w16, svuint8x4_t,
+ z28 = svreadz_ver_za8_u8_vg4 (0, w16),
+ z28 = svreadz_ver_za8_u8_vg4 (0, w16))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svfloat16x2_t,
+ z0 = svreadz_za16_f16_vg1x2 (0),
+ z0 = svreadz_za16_f16_vg1x2 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svint16x2_t,
+ z0 = svreadz_za16_s16_vg1x2 (w0),
+ z0 = svreadz_za16_s16_vg1x2 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svuint16x2_t,
+ z0 = svreadz_za16_u16_vg1x2 (w7),
+ z0 = svreadz_za16_u16_vg1x2 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svbfloat16x2_t,
+ z0 = svreadz_za16_bf16_vg1x2 (w8),
+ z0 = svreadz_za16_bf16_vg1x2 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w11, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svint16x2_t,
+ z0 = svreadz_za16_s16_vg1x2 (w11),
+ z0 = svreadz_za16_s16_vg1x2 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svuint16x2_t,
+ z0 = svreadz_za16_u16_vg1x2 (w12),
+ z0 = svreadz_za16_u16_vg1x2 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 7, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svfloat16x2_t,
+ z0 = svreadz_za16_f16_vg1x2 (w8 + 7),
+ z0 = svreadz_za16_f16_vg1x2 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svint16x2_t,
+ z0 = svreadz_za16_s16_vg1x2 (w8 + 8),
+ z0 = svreadz_za16_s16_vg1x2 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svuint16x2_t,
+ z0 = svreadz_za16_u16_vg1x2 (w8 - 1),
+ z0 = svreadz_za16_u16_vg1x2 (w8 - 1))
+
+/*
+** readz_w8_z18:
+** movaz {z18\.d - z19\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svfloat16x2_t,
+ z18 = svreadz_za16_f16_vg1x2 (w8),
+ z18 = svreadz_za16_f16_vg1x2 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx2\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svint16x2_t,
+ z23 = svreadz_za16_s16_vg1x2 (w8),
+ z23 = svreadz_za16_s16_vg1x2 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z29\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svbfloat16x2_t,
+ z28 = svreadz_za16_bf16_vg1x2 (w8),
+ z28 = svreadz_za16_bf16_vg1x2 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svint16x4_t,
+ z0 = svreadz_za16_s16_vg1x4 (0),
+ z0 = svreadz_za16_s16_vg1x4 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svuint16x4_t,
+ z0 = svreadz_za16_u16_vg1x4 (w0),
+ z0 = svreadz_za16_u16_vg1x4 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svfloat16x4_t,
+ z0 = svreadz_za16_f16_vg1x4 (w7),
+ z0 = svreadz_za16_f16_vg1x4 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svint16x4_t,
+ z0 = svreadz_za16_s16_vg1x4 (w8),
+ z0 = svreadz_za16_s16_vg1x4 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w11, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svuint16x4_t,
+ z0 = svreadz_za16_u16_vg1x4 (w11),
+ z0 = svreadz_za16_u16_vg1x4 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svbfloat16x4_t,
+ z0 = svreadz_za16_bf16_vg1x4 (w12),
+ z0 = svreadz_za16_bf16_vg1x4 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 7, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svint16x4_t,
+ z0 = svreadz_za16_s16_vg1x4 (w8 + 7),
+ z0 = svreadz_za16_s16_vg1x4 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svuint16x4_t,
+ z0 = svreadz_za16_u16_vg1x4 (w8 + 8),
+ z0 = svreadz_za16_u16_vg1x4 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svfloat16x4_t,
+ z0 = svreadz_za16_f16_vg1x4 (w8 - 1),
+ z0 = svreadz_za16_f16_vg1x4 (w8 - 1))
+
+/*
+** readz_w8_z4:
+** movaz {z4\.d - z7\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z4, svint16x4_t,
+ z4 = svreadz_za16_s16_vg1x4 (w8),
+ z4 = svreadz_za16_s16_vg1x4 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z18:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svuint16x4_t,
+ z18 = svreadz_za16_u16_vg1x4 (w8),
+ z18 = svreadz_za16_u16_vg1x4 (w8))
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svbfloat16x4_t,
+ z23 = svreadz_za16_bf16_vg1x4 (w8),
+ z23 = svreadz_za16_bf16_vg1x4 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z31\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svint16x4_t,
+ z28 = svreadz_za16_s16_vg1x4 (w8),
+ z28 = svreadz_za16_s16_vg1x4 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svfloat32x2_t,
+ z0 = svreadz_za32_f32_vg1x2 (0),
+ z0 = svreadz_za32_f32_vg1x2 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svint32x2_t,
+ z0 = svreadz_za32_s32_vg1x2 (w0),
+ z0 = svreadz_za32_s32_vg1x2 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svuint32x2_t,
+ z0 = svreadz_za32_u32_vg1x2 (w7),
+ z0 = svreadz_za32_u32_vg1x2 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svfloat32x2_t,
+ z0 = svreadz_za32_f32_vg1x2 (w8),
+ z0 = svreadz_za32_f32_vg1x2 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w11, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svint32x2_t,
+ z0 = svreadz_za32_s32_vg1x2 (w11),
+ z0 = svreadz_za32_s32_vg1x2 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svuint32x2_t,
+ z0 = svreadz_za32_u32_vg1x2 (w12),
+ z0 = svreadz_za32_u32_vg1x2 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 7, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svfloat32x2_t,
+ z0 = svreadz_za32_f32_vg1x2 (w8 + 7),
+ z0 = svreadz_za32_f32_vg1x2 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svint32x2_t,
+ z0 = svreadz_za32_s32_vg1x2 (w8 + 8),
+ z0 = svreadz_za32_s32_vg1x2 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svuint32x2_t,
+ z0 = svreadz_za32_u32_vg1x2 (w8 - 1),
+ z0 = svreadz_za32_u32_vg1x2 (w8 - 1))
+
+/*
+** readz_w8_z18:
+** movaz {z18\.d - z19\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svfloat32x2_t,
+ z18 = svreadz_za32_f32_vg1x2 (w8),
+ z18 = svreadz_za32_f32_vg1x2 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx2\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svint32x2_t,
+ z23 = svreadz_za32_s32_vg1x2 (w8),
+ z23 = svreadz_za32_s32_vg1x2 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z29\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svuint32x2_t,
+ z28 = svreadz_za32_u32_vg1x2 (w8),
+ z28 = svreadz_za32_u32_vg1x2 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svint32x4_t,
+ z0 = svreadz_za32_s32_vg1x4 (0),
+ z0 = svreadz_za32_s32_vg1x4 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svuint32x4_t,
+ z0 = svreadz_za32_u32_vg1x4 (w0),
+ z0 = svreadz_za32_u32_vg1x4 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svfloat32x4_t,
+ z0 = svreadz_za32_f32_vg1x4 (w7),
+ z0 = svreadz_za32_f32_vg1x4 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svint32x4_t,
+ z0 = svreadz_za32_s32_vg1x4 (w8),
+ z0 = svreadz_za32_s32_vg1x4 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w11, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svuint32x4_t,
+ z0 = svreadz_za32_u32_vg1x4 (w11),
+ z0 = svreadz_za32_u32_vg1x4 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svfloat32x4_t,
+ z0 = svreadz_za32_f32_vg1x4 (w12),
+ z0 = svreadz_za32_f32_vg1x4 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 7, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svint32x4_t,
+ z0 = svreadz_za32_s32_vg1x4 (w8 + 7),
+ z0 = svreadz_za32_s32_vg1x4 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svuint32x4_t,
+ z0 = svreadz_za32_u32_vg1x4 (w8 + 8),
+ z0 = svreadz_za32_u32_vg1x4 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svfloat32x4_t,
+ z0 = svreadz_za32_f32_vg1x4 (w8 - 1),
+ z0 = svreadz_za32_f32_vg1x4 (w8 - 1))
+
+/*
+** readz_w8_z4:
+** movaz {z4\.d - z7\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z4, svint32x4_t,
+ z4 = svreadz_za32_s32_vg1x4 (w8),
+ z4 = svreadz_za32_s32_vg1x4 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z18:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svuint32x4_t,
+ z18 = svreadz_za32_u32_vg1x4 (w8),
+ z18 = svreadz_za32_u32_vg1x4 (w8))
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svfloat32x4_t,
+ z23 = svreadz_za32_f32_vg1x4 (w8),
+ z23 = svreadz_za32_f32_vg1x4 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z31\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svint32x4_t,
+ z28 = svreadz_za32_s32_vg1x4 (w8),
+ z28 = svreadz_za32_s32_vg1x4 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svfloat64x2_t,
+ z0 = svreadz_za64_f64_vg1x2 (0),
+ z0 = svreadz_za64_f64_vg1x2 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svint64x2_t,
+ z0 = svreadz_za64_s64_vg1x2 (w0),
+ z0 = svreadz_za64_s64_vg1x2 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svuint64x2_t,
+ z0 = svreadz_za64_u64_vg1x2 (w7),
+ z0 = svreadz_za64_u64_vg1x2 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svfloat64x2_t,
+ z0 = svreadz_za64_f64_vg1x2 (w8),
+ z0 = svreadz_za64_f64_vg1x2 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w11, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svint64x2_t,
+ z0 = svreadz_za64_s64_vg1x2 (w11),
+ z0 = svreadz_za64_s64_vg1x2 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svuint64x2_t,
+ z0 = svreadz_za64_u64_vg1x2 (w12),
+ z0 = svreadz_za64_u64_vg1x2 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 7, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svfloat64x2_t,
+ z0 = svreadz_za64_f64_vg1x2 (w8 + 7),
+ z0 = svreadz_za64_f64_vg1x2 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svint64x2_t,
+ z0 = svreadz_za64_s64_vg1x2 (w8 + 8),
+ z0 = svreadz_za64_s64_vg1x2 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svuint64x2_t,
+ z0 = svreadz_za64_u64_vg1x2 (w8 - 1),
+ z0 = svreadz_za64_u64_vg1x2 (w8 - 1))
+
+/*
+** readz_w8_z18:
+** movaz {z18\.d - z19\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svfloat64x2_t,
+ z18 = svreadz_za64_f64_vg1x2 (w8),
+ z18 = svreadz_za64_f64_vg1x2 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx2\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svint64x2_t,
+ z23 = svreadz_za64_s64_vg1x2 (w8),
+ z23 = svreadz_za64_s64_vg1x2 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z29\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svuint64x2_t,
+ z28 = svreadz_za64_u64_vg1x2 (w8),
+ z28 = svreadz_za64_u64_vg1x2 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svint64x4_t,
+ z0 = svreadz_za64_s64_vg1x4 (0),
+ z0 = svreadz_za64_s64_vg1x4 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svuint64x4_t,
+ z0 = svreadz_za64_u64_vg1x4 (w0),
+ z0 = svreadz_za64_u64_vg1x4 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svfloat64x4_t,
+ z0 = svreadz_za64_f64_vg1x4 (w7),
+ z0 = svreadz_za64_f64_vg1x4 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svint64x4_t,
+ z0 = svreadz_za64_s64_vg1x4 (w8),
+ z0 = svreadz_za64_s64_vg1x4 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w11, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svuint64x4_t,
+ z0 = svreadz_za64_u64_vg1x4 (w11),
+ z0 = svreadz_za64_u64_vg1x4 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svfloat64x4_t,
+ z0 = svreadz_za64_f64_vg1x4 (w12),
+ z0 = svreadz_za64_f64_vg1x4 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 7, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svint64x4_t,
+ z0 = svreadz_za64_s64_vg1x4 (w8 + 7),
+ z0 = svreadz_za64_s64_vg1x4 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svuint64x4_t,
+ z0 = svreadz_za64_u64_vg1x4 (w8 + 8),
+ z0 = svreadz_za64_u64_vg1x4 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svfloat64x4_t,
+ z0 = svreadz_za64_f64_vg1x4 (w8 - 1),
+ z0 = svreadz_za64_f64_vg1x4 (w8 - 1))
+
+/*
+** readz_w8_z4:
+** movaz {z4\.d - z7\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z4, svint64x4_t,
+ z4 = svreadz_za64_s64_vg1x4 (w8),
+ z4 = svreadz_za64_s64_vg1x4 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z18:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svuint64x4_t,
+ z18 = svreadz_za64_u64_vg1x4 (w8),
+ z18 = svreadz_za64_u64_vg1x4 (w8))
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svfloat64x4_t,
+ z23 = svreadz_za64_f64_vg1x4 (w8),
+ z23 = svreadz_za64_f64_vg1x4 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z31\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svint64x4_t,
+ z28 = svreadz_za64_s64_vg1x4 (w8),
+ z28 = svreadz_za64_s64_vg1x4 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (0),
+ z0 = svreadz_za8_s8_vg1x2 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (w0),
+ z0 = svreadz_za8_s8_vg1x2 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svuint8x2_t,
+ z0 = svreadz_za8_u8_vg1x2 (w7),
+ z0 = svreadz_za8_u8_vg1x2 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (w8),
+ z0 = svreadz_za8_s8_vg1x2 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w11, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (w11),
+ z0 = svreadz_za8_s8_vg1x2 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svuint8x2_t,
+ z0 = svreadz_za8_u8_vg1x2 (w12),
+ z0 = svreadz_za8_u8_vg1x2 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z1\.d}, za\.d\[w8, 7, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (w8 + 7),
+ z0 = svreadz_za8_s8_vg1x2 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svint8x2_t,
+ z0 = svreadz_za8_s8_vg1x2 (w8 + 8),
+ z0 = svreadz_za8_s8_vg1x2 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z1\.d}, za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svuint8x2_t,
+ z0 = svreadz_za8_u8_vg1x2 (w8 - 1),
+ z0 = svreadz_za8_u8_vg1x2 (w8 - 1))
+
+/*
+** readz_w8_z18:
+** movaz {z18\.d - z19\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svuint8x2_t,
+ z18 = svreadz_za8_u8_vg1x2 (w8),
+ z18 = svreadz_za8_u8_vg1x2 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx2\]
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svint8x2_t,
+ z23 = svreadz_za8_s8_vg1x2 (w8),
+ z23 = svreadz_za8_s8_vg1x2 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z29\.d}, za\.d\[w8, 0, vgx2\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svuint8x2_t,
+ z28 = svreadz_za8_u8_vg1x2 (w8),
+ z28 = svreadz_za8_u8_vg1x2 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** readz_0_z0:
+** mov (w8|w9|w10|w11), #?0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_0_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (0),
+ z0 = svreadz_za8_s8_vg1x4 (0))
+
+/*
+** readz_w0_z0:
+** mov (w8|w9|w10|w11), w0
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w0_z0, svuint8x4_t,
+ z0 = svreadz_za8_u8_vg1x4 (w0),
+ z0 = svreadz_za8_u8_vg1x4 (w0))
+
+/*
+** readz_w7_z0:
+** mov (w8|w9|w10|w11), w7
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w7_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (w7),
+ z0 = svreadz_za8_s8_vg1x4 (w7))
+
+/*
+** readz_w8_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (w8),
+ z0 = svreadz_za8_s8_vg1x4 (w8))
+
+/*
+** readz_w11_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w11, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w11_z0, svuint8x4_t,
+ z0 = svreadz_za8_u8_vg1x4 (w11),
+ z0 = svreadz_za8_u8_vg1x4 (w11))
+
+
+/*
+** readz_w12_z0:
+** mov (w8|w9|w10|w11), w12
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w12_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (w12),
+ z0 = svreadz_za8_s8_vg1x4 (w12))
+
+/*
+** readz_w8p7_z0:
+** movaz {z0\.d - z3\.d}, za\.d\[w8, 7, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p7_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (w8 + 7),
+ z0 = svreadz_za8_s8_vg1x4 (w8 + 7))
+
+/*
+** readz_w8p8_z0:
+** add (w8|w9|w10|w11), w8, #?8
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8p8_z0, svuint8x4_t,
+ z0 = svreadz_za8_u8_vg1x4 (w8 + 8),
+ z0 = svreadz_za8_u8_vg1x4 (w8 + 8))
+
+/*
+** readz_w8m1_z0:
+** sub (w8|w9|w10|w11), w8, #?1
+** movaz {z0\.d - z3\.d}, za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8m1_z0, svint8x4_t,
+ z0 = svreadz_za8_s8_vg1x4 (w8 - 1),
+ z0 = svreadz_za8_s8_vg1x4 (w8 - 1))
+
+/*
+** readz_w8_z4:
+** movaz {z4\.d - z7\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z4, svint8x4_t,
+ z4 = svreadz_za8_s8_vg1x4 (w8),
+ z4 = svreadz_za8_s8_vg1x4 (w8))
+
+/* Leave the assembler to check for correctness for misaligned registers. */
+
+/*
+** readz_w8_z18:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z18, svuint8x4_t,
+ z18 = svreadz_za8_u8_vg1x4 (w8),
+ z18 = svreadz_za8_u8_vg1x4 (w8))
+
+/*
+** readz_w8_z23:
+** movaz [^\n]+, za\.d\[w8, 0, vgx4\]
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** mov [^\n]+
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z23, svuint8x4_t,
+ z23 = svreadz_za8_u8_vg1x4 (w8),
+ z23 = svreadz_za8_u8_vg1x4 (w8))
+
+/*
+** readz_w8_z28:
+** movaz {z28\.d - z31\.d}, za\.d\[w8, 0, vgx4\]
+** ret
+*/
+TEST_READ_ZA_XN (readz_w8_z28, svint8x4_t,
+ z28 = svreadz_za8_s8_vg1x4 (w8),
+ z28 = svreadz_za8_s8_vg1x4 (w8))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg1x2 (0),
+ svzero_za64_vg1x2 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg1x2 (w0),
+ svzero_za64_vg1x2 (w0))
+
+/*
+** zero_w0p1:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg1x2 (w0 + 1),
+ svzero_za64_vg1x2 (w0 + 1))
+
+/*
+** zero_w0p2:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 2, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg1x2 (w0 + 2),
+ svzero_za64_vg1x2 (w0 + 2))
+
+/*
+** zero_w0p3:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg1x2 (w0 + 3),
+ svzero_za64_vg1x2 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg1x2 (w0 + 4),
+ svzero_za64_vg1x2 (w0 + 4))
+
+/*
+** zero_w0p7:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 7, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p7, svint8_t,
+ svzero_za64_vg1x2 (w0 + 7),
+ svzero_za64_vg1x2 (w0 + 7))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg1x2 (w0 + 8),
+ svzero_za64_vg1x2 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg1x2 (w0 - 1),
+ svzero_za64_vg1x2 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg1x4 (0),
+ svzero_za64_vg1x4 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg1x4 (w0),
+ svzero_za64_vg1x4 (w0))
+
+/*
+** zero_w0p1:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg1x4 (w0 + 1),
+ svzero_za64_vg1x4 (w0 + 1))
+
+/*
+** zero_w0p2:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 2, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg1x4 (w0 + 2),
+ svzero_za64_vg1x4 (w0 + 2))
+
+/*
+** zero_w0p3:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg1x4 (w0 + 3),
+ svzero_za64_vg1x4 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg1x4 (w0 + 4),
+ svzero_za64_vg1x4 (w0 + 4))
+
+/*
+** zero_w0p7:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 7, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p7, svint8_t,
+ svzero_za64_vg1x4 (w0 + 7),
+ svzero_za64_vg1x4 (w0 + 7))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg1x4 (w0 + 8),
+ svzero_za64_vg1x4 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg1x4 (w0 - 1),
+ svzero_za64_vg1x4 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg2x1 (0),
+ svzero_za64_vg2x1 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg2x1 (w0),
+ svzero_za64_vg2x1 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg2x1 (w0 + 1),
+ svzero_za64_vg2x1 (w0 + 1))
+
+/*
+** zero_w0p2:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 2:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg2x1 (w0 + 2),
+ svzero_za64_vg2x1 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg2x1 (w0 + 3),
+ svzero_za64_vg2x1 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:5\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg2x1 (w0 + 4),
+ svzero_za64_vg2x1 (w0 + 4))
+
+/*
+** zero_w0p6:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 6:7\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg2x1 (w0 + 6),
+ svzero_za64_vg2x1 (w0 + 6))
+
+/*
+** zero_w0p8:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 8:9\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg2x1 (w0 + 8),
+ svzero_za64_vg2x1 (w0 + 8))
+
+/*
+** zero_w0p14:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 14:15\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p14, svint8_t,
+ svzero_za64_vg2x1 (w0 + 14),
+ svzero_za64_vg2x1 (w0 + 14))
+
+/*
+** zero_w0p16:
+** add (w8|w9|w10|w11), w0, #?16
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p16, svint8_t,
+ svzero_za64_vg2x1 (w0 + 16),
+ svzero_za64_vg2x1 (w0 + 16))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg2x1 (w0 - 1),
+ svzero_za64_vg2x1 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg2x2 (0),
+ svzero_za64_vg2x2 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg2x2 (w0),
+ svzero_za64_vg2x2 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg2x2 (w0 + 1),
+ svzero_za64_vg2x2 (w0 + 1))
+
+/*
+** zero_w0p2:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 2:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg2x2 (w0 + 2),
+ svzero_za64_vg2x2 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg2x2 (w0 + 3),
+ svzero_za64_vg2x2 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:5, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg2x2 (w0 + 4),
+ svzero_za64_vg2x2 (w0 + 4))
+
+/*
+** zero_w0p6:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 6:7, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg2x2 (w0 + 6),
+ svzero_za64_vg2x2 (w0 + 6))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg2x2 (w0 + 8),
+ svzero_za64_vg2x2 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg2x2 (w0 - 1),
+ svzero_za64_vg2x2 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg2x4 (0),
+ svzero_za64_vg2x4 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg2x4 (w0),
+ svzero_za64_vg2x4 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg2x4 (w0 + 1),
+ svzero_za64_vg2x4 (w0 + 1))
+
+/*
+** zero_w0p2:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 2:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg2x4 (w0 + 2),
+ svzero_za64_vg2x4 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg2x4 (w0 + 3),
+ svzero_za64_vg2x4 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:5, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg2x4 (w0 + 4),
+ svzero_za64_vg2x4 (w0 + 4))
+
+/*
+** zero_w0p6:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 6:7, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg2x4 (w0 + 6),
+ svzero_za64_vg2x4 (w0 + 6))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg2x4 (w0 + 8),
+ svzero_za64_vg2x4 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:1, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg2x4 (w0 - 1),
+ svzero_za64_vg2x4 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg4x1 (0),
+ svzero_za64_vg4x1 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg4x1 (w0),
+ svzero_za64_vg4x1 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg4x1 (w0 + 1),
+ svzero_za64_vg4x1 (w0 + 1))
+
+/*
+** zero_w0p2:
+** add (w8|w9|w10|w11), w0, #?2
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg4x1 (w0 + 2),
+ svzero_za64_vg4x1 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg4x1 (w0 + 3),
+ svzero_za64_vg4x1 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:7\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg4x1 (w0 + 4),
+ svzero_za64_vg4x1 (w0 + 4))
+
+/*
+** zero_w0p6:
+** add (w8|w9|w10|w11), w0, #?6
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg4x1 (w0 + 6),
+ svzero_za64_vg4x1 (w0 + 6))
+
+/*
+** zero_w0p8:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 8:11\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg4x1 (w0 + 8),
+ svzero_za64_vg4x1 (w0 + 8))
+
+/*
+** zero_w0p12:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 12:15\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p12, svint8_t,
+ svzero_za64_vg4x1 (w0 + 12),
+ svzero_za64_vg4x1 (w0 + 12))
+
+/*
+** zero_w0p14:
+** add (w8|w9|w10|w11), w0, #?14
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p14, svint8_t,
+ svzero_za64_vg4x1 (w0 + 14),
+ svzero_za64_vg4x1 (w0 + 14))
+
+/*
+** zero_w0p16:
+** add (w8|w9|w10|w11), w0, #?16
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p16, svint8_t,
+ svzero_za64_vg4x1 (w0 + 16),
+ svzero_za64_vg4x1 (w0 + 16))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg4x1 (w0 - 1),
+ svzero_za64_vg4x1 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg4x2 (0),
+ svzero_za64_vg4x2 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg4x2 (w0),
+ svzero_za64_vg4x2 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg4x2 (w0 + 1),
+ svzero_za64_vg4x2 (w0 + 1))
+
+/*
+** zero_w0p2:
+** add (w8|w9|w10|w11), w0, #?2
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg4x2 (w0 + 2),
+ svzero_za64_vg4x2 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg4x2 (w0 + 3),
+ svzero_za64_vg4x2 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:7, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg4x2 (w0 + 4),
+ svzero_za64_vg4x2 (w0 + 4))
+
+/*
+** zero_w0p6:
+** add (w8|w9|w10|w11), w0, #?6
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg4x2 (w0 + 6),
+ svzero_za64_vg4x2 (w0 + 6))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg4x2 (w0 + 8),
+ svzero_za64_vg4x2 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3, vgx2\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg4x2 (w0 - 1),
+ svzero_za64_vg4x2 (w0 - 1))
--- /dev/null
+/* { dg-do assemble { target aarch64_asm_sme2p1_ok } } */
+/* { dg-do compile { target { ! aarch64_asm_sme2p1_ok } } } */
+/* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
+
+#include "test_sme2_acle.h"
+
+#pragma GCC target "+sme2p1"
+
+/*
+** zero_0:
+** mov (w8|w9|w10|w11), #?0
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_0, svint8_t,
+ svzero_za64_vg4x4 (0),
+ svzero_za64_vg4x4 (0))
+
+/*
+** zero_w0:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0, svint8_t,
+ svzero_za64_vg4x4 (w0),
+ svzero_za64_vg4x4 (w0))
+
+/*
+** zero_w0p1:
+** add (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p1, svint8_t,
+ svzero_za64_vg4x4 (w0 + 1),
+ svzero_za64_vg4x4 (w0 + 1))
+
+/*
+** zero_w0p2:
+** add (w8|w9|w10|w11), w0, #?2
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p2, svint8_t,
+ svzero_za64_vg4x4 (w0 + 2),
+ svzero_za64_vg4x4 (w0 + 2))
+
+/*
+** zero_w0p3:
+** add (w8|w9|w10|w11), w0, #?3
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p3, svint8_t,
+ svzero_za64_vg4x4 (w0 + 3),
+ svzero_za64_vg4x4 (w0 + 3))
+
+/*
+** zero_w0p4:
+** mov (w8|w9|w10|w11), w0
+** zero za\.d\[\1, 4:7, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p4, svint8_t,
+ svzero_za64_vg4x4 (w0 + 4),
+ svzero_za64_vg4x4 (w0 + 4))
+
+/*
+** zero_w0p6:
+** add (w8|w9|w10|w11), w0, #?6
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p6, svint8_t,
+ svzero_za64_vg4x4 (w0 + 6),
+ svzero_za64_vg4x4 (w0 + 6))
+
+/*
+** zero_w0p8:
+** add (w8|w9|w10|w11), w0, #?8
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0p8, svint8_t,
+ svzero_za64_vg4x4 (w0 + 8),
+ svzero_za64_vg4x4 (w0 + 8))
+
+/*
+** zero_w0m1:
+** sub (w8|w9|w10|w11), w0, #?1
+** zero za\.d\[\1, 0:3, vgx4\]
+** ret
+*/
+TEST_ZA_XN (zero_w0m1, svint8_t,
+ svzero_za64_vg4x4 (w0 - 1),
+ svzero_za64_vg4x4 (w0 - 1))
foreach { aarch64_ext } { "fp" "simd" "crypto" "crc" "lse" "dotprod" "sve"
"i8mm" "f32mm" "f64mm" "bf16" "sb" "sve2" "ls64"
"sme" "sme-i16i64" "sme2" "sve-b16b16"
- "sme-b16b16" "sme-f16f16" } {
+ "sme-b16b16" "sme-f16f16" "sme2p1" } {
eval [string map [list FUNC $aarch64_ext] {
proc check_effective_target_aarch64_asm_FUNC_ok { } {
if { [istarget aarch64*-*-*] } {
projects / thirdparty / gcc.git / commitdiff
