;; code for that case. But we don't reject the possibility.
(define_expand "extendsidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
- ""
- "")
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))])
(define_insn "*cvtlq"
[(set (match_operand:DI 0 "register_operand" "=f")
(set_attr "length" "*,*,8")])
(define_split
- [(set (match_operand:DI 0 "hard_fp_register_operand" "")
- (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
+ [(set (match_operand:DI 0 "hard_fp_register_operand")
+ (sign_extend:DI (match_operand:SI 1 "memory_operand")))]
"reload_completed"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
;; reload when converting fp->int.
(define_peephole2
- [(set (match_operand:SI 0 "hard_int_register_operand" "")
- (match_operand:SI 1 "memory_operand" ""))
- (set (match_operand:DI 2 "hard_int_register_operand" "")
+ [(set (match_operand:SI 0 "hard_int_register_operand")
+ (match_operand:SI 1 "memory_operand"))
+ (set (match_operand:DI 2 "hard_int_register_operand")
(sign_extend:DI (match_dup 0)))]
"true_regnum (operands[0]) == true_regnum (operands[2])
|| peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2)
- (sign_extend:DI (match_dup 1)))]
- "")
+ (sign_extend:DI (match_dup 1)))])
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
ldah %0,%h2(%r1)")
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (plus:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (plus:SI (match_operand:SI 1 "register_operand")
+ (match_operand:SI 2 "const_int_operand")))]
"! add_operand (operands[2], SImode)"
[(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
subl %r1,%n2,%0")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI
- (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))))
- (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
+ (plus:SI (match_operand:SI 1 "reg_not_elim_operand")
+ (match_operand:SI 2 "const_int_operand"))))
+ (clobber (match_operand:SI 3 "reg_not_elim_operand"))]
"! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) % 4 == 0"
[(set (match_dup 3) (match_dup 4))
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI
(plus:SI (match_operator:SI 1 "comparison_operator"
- [(match_operand 2 "" "")
- (match_operand 3 "" "")])
- (match_operand:SI 4 "add_operand" ""))))
- (clobber (match_operand:DI 5 "register_operand" ""))]
+ [(match_operand 2)
+ (match_operand 3)])
+ (match_operand:SI 4 "add_operand"))))
+ (clobber (match_operand:DI 5 "register_operand"))]
""
[(set (match_dup 5) (match_dup 6))
(set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
})
(define_expand "adddi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "add_operand" "")))]
- ""
- "")
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "add_operand")))])
(define_insn "*adddi_er_lo16_dtp"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
+ (match_operand:DI 2 "dtp16_symbolic_operand")))]
"HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!dtprel")
(define_insn "*adddi_er_hi32_dtp"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
- (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
+ (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))]
"HAVE_AS_TLS"
"ldah %0,%2(%1)\t\t!dtprelhi")
(define_insn "*adddi_er_lo32_dtp"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
+ (match_operand:DI 2 "dtp32_symbolic_operand")))]
"HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!dtprello")
(define_insn "*adddi_er_lo16_tp"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "tp16_symbolic_operand" "")))]
+ (match_operand:DI 2 "tp16_symbolic_operand")))]
"HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!tprel")
(define_insn "*adddi_er_hi32_tp"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
- (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
+ (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))]
"HAVE_AS_TLS"
"ldah %0,%2(%1)\t\t!tprelhi")
(define_insn "*adddi_er_lo32_tp"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "tp32_symbolic_operand" "")))]
+ (match_operand:DI 2 "tp32_symbolic_operand")))]
"HAVE_AS_TLS"
"lda %0,%2(%1)\t\t!tprello")
(define_insn "*adddi_er_high_l"
[(set (match_operand:DI 0 "register_operand" "=r")
(plus:DI (match_operand:DI 1 "register_operand" "r")
- (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
+ (high:DI (match_operand:DI 2 "local_symbolic_operand"))))]
"TARGET_EXPLICIT_RELOCS && reload_completed"
"ldah %0,%2(%1)\t\t!gprelhigh"
[(set_attr "usegp" "yes")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (high:DI (match_operand:DI 1 "local_symbolic_operand")))]
"TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0)
(plus:DI (match_dup 2) (high:DI (match_dup 1))))]
;; Don't do this if we are adjusting SP since we don't want to do it
;; in two steps. Don't split FP sources for the reason listed above.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (plus:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "const_int_operand")))]
"! add_operand (operands[2], DImode)
&& operands[0] != stack_pointer_rtx
&& operands[1] != frame_pointer_rtx
s%2subl %1,%n3,%0")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(sign_extend:DI
(plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
- [(match_operand 2 "" "")
- (match_operand 3 "" "")])
- (match_operand:SI 4 "const48_operand" ""))
- (match_operand:SI 5 "sext_add_operand" ""))))
- (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
+ [(match_operand 2)
+ (match_operand 3)])
+ (match_operand:SI 4 "const48_operand"))
+ (match_operand:SI 5 "sext_add_operand"))))
+ (clobber (match_operand:DI 6 "reg_not_elim_operand"))]
""
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
(define_insn "*subsi_se"
[(set (match_operand:DI 0 "register_operand" "=r")
- (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
- (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
+ (sign_extend:DI
+ (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
+ (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
""
"subl %r1,%2,%0")
(set_attr "opsize" "<mode>")])
(define_expand "umuldi3_highpart"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI
- (match_operand:DI 1 "register_operand" ""))
- (match_operand:DI 2 "reg_or_8bit_operand" ""))
+ (match_operand:DI 1 "register_operand"))
+ (match_operand:DI 2 "reg_or_8bit_operand"))
(const_int 64))))]
""
{
(define_expand "<code>si3"
[(set (match_dup 3)
- (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
+ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))
(set (match_dup 4)
- (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
+ (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand")))
(parallel [(set (match_dup 5)
(sign_extend:DI
(any_divmod:SI (match_dup 3) (match_dup 4))))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])
- (set (match_operand:SI 0 "nonimmediate_operand" "")
+ (set (match_operand:SI 0 "nonimmediate_operand")
(subreg:SI (match_dup 5) 0))]
"TARGET_ABI_OSF"
{
})
(define_expand "<code>di3"
- [(parallel [(set (match_operand:DI 0 "register_operand" "")
+ [(parallel [(set (match_operand:DI 0 "register_operand")
(any_divmod:DI
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "register_operand" "")))
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "register_operand")))
(clobber (reg:DI 23))
(clobber (reg:DI 28))])]
- "TARGET_ABI_OSF"
- "")
+ "TARGET_ABI_OSF")
;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
;; expanded by the assembler.
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")])))
(use (match_operand:DI 4 "register_operand" "c"))
- (use (match_operand 5 "const_int_operand" ""))
+ (use (match_operand 5 "const_int_operand"))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
[(match_operand:DI 1 "register_operand" "a")
(match_operand:DI 2 "register_operand" "b")]))
(use (match_operand:DI 4 "register_operand" "c"))
- (use (match_operand 5 "const_int_operand" ""))
+ (use (match_operand 5 "const_int_operand"))
(clobber (reg:DI 23))
(clobber (reg:DI 28))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
;; too messy otherwise.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "const_int_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (and:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "const_int_operand")))]
"HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
[(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
(define_expand "ffsdi2"
[(set (match_dup 2)
- (ctz:DI (match_operand:DI 1 "register_operand" "")))
+ (ctz:DI (match_operand:DI 1 "register_operand")))
(set (match_dup 3)
(plus:DI (match_dup 2) (const_int 1)))
- (set (match_operand:DI 0 "register_operand" "")
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 1) (const_int 0))
(const_int 0) (match_dup 3)))]
"TARGET_CIX"
[(set_attr "type" "mvi")])
(define_expand "bswapsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (bswap:SI (match_operand:SI 1 "register_operand" "")))]
+ [(set (match_operand:SI 0 "register_operand")
+ (bswap:SI (match_operand:SI 1 "register_operand")))]
"!optimize_size"
{
rtx t0, t1;
})
(define_expand "bswapdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (bswap:DI (match_operand:DI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (bswap:DI (match_operand:DI 1 "register_operand")))]
"!optimize_size"
{
rtx t0, t1;
[(set_attr "type" "shift")])
(define_expand "extendqidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:QI 1 "some_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:QI 1 "some_operand")))]
""
{
if (TARGET_BWX)
[(set_attr "type" "shift")])
(define_expand "extendhidi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extend:DI (match_operand:HI 1 "some_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extend:DI (match_operand:HI 1 "some_operand")))]
""
{
if (TARGET_BWX)
(define_expand "unaligned_extendqidi"
[(set (match_dup 3)
- (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8))))
+ (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
(set (match_dup 4)
(ashift:DI (match_dup 3)
(minus:DI (const_int 64)
(ashift:DI
(and:DI (match_dup 2) (const_int 7))
(const_int 3)))))
- (set (match_operand:QI 0 "register_operand" "")
+ (set (match_operand:QI 0 "register_operand")
(ashiftrt:DI (match_dup 4) (const_int 56)))]
""
{
(define_expand "unaligned_extendhidi"
[(set (match_dup 3)
- (mem:DI (and:DI (match_operand:DI 1 "address_operand" "") (const_int -8))))
+ (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8))))
(set (match_dup 4)
(ashift:DI (match_dup 3)
(minus:DI (const_int 64)
(ashift:DI
(and:DI (match_dup 2) (const_int 7))
(const_int 3)))))
- (set (match_operand:HI 0 "register_operand" "")
+ (set (match_operand:HI 0 "register_operand")
(ashiftrt:DI (match_dup 4) (const_int 48)))]
""
{
(define_insn "extxl"
[(set (match_operand:DI 0 "register_operand" "=r")
- (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
- (match_operand:DI 2 "mode_width_operand" "n")
- (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
- (const_int 3))))]
+ (zero_extract:DI
+ (match_operand:DI 1 "reg_or_0_operand" "rJ")
+ (match_operand:DI 2 "mode_width_operand" "n")
+ (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
+ (const_int 3))))]
""
"ext%M2l %r1,%3,%0"
[(set_attr "type" "shift")])
;; to the address calculation.
;;(define_split
-;; [(set (match_operand:DI 0 "register_operand" "")
-;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
-;; (match_operand:DI 2 "mode_width_operand" "")
-;; (ashift:DI (match_operand:DI 3 "" "")
+;; [(set (match_operand:DI 0 "register_operand")
+;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand")
+;; (match_operand:DI 2 "mode_width_operand")
+;; (ashift:DI (match_operand:DI 3)
;; (const_int 3)))
-;; (match_operand:DI 4 "const_int_operand" "")))
-;; (clobber (match_operand:DI 5 "register_operand" ""))]
+;; (match_operand:DI 4 "const_int_operand")))
+;; (clobber (match_operand:DI 5 "register_operand"))]
;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
;; [(set (match_dup 5) (match_dup 6))
;; (set (match_dup 0)
[(set_attr "type" "fadd")])
(define_expand "abstf2"
- [(parallel [(set (match_operand:TF 0 "register_operand" "")
- (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
+ [(parallel [(set (match_operand:TF 0 "register_operand")
+ (abs:TF (match_operand:TF 1 "reg_or_0_operand")))
(use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS"
{
[(set_attr "type" "fadd")])
(define_expand "negtf2"
- [(parallel [(set (match_operand:TF 0 "register_operand" "")
- (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
+ [(parallel [(set (match_operand:TF 0 "register_operand")
+ (neg:TF (match_operand:TF 1 "reg_or_0_operand")))
(use (match_dup 2))])]
"TARGET_HAS_XFLOATING_LIBS"
{
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "addtf3"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))
- (use (match_operand:TF 2 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))
+ (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (PLUS, operands); DONE;")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "subtf3"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))
- (use (match_operand:TF 2 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))
+ (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MINUS, operands); DONE;")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "multf3"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))
- (use (match_operand:TF 2 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))
+ (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (MULT, operands); DONE;")
(define_insn "*divdf_ext3"
[(set (match_operand:DF 0 "register_operand" "=f")
- (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
- (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
+ (div:DF (float_extend:DF
+ (match_operand:SF 1 "reg_or_0_operand" "fG"))
+ (float_extend:DF
+ (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
"div%-%/ %R1,%R2,%0"
[(set_attr "type" "fdiv")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "divtf3"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))
- (use (match_operand:TF 2 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))
+ (use (match_operand:TF 2 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_arith (DIV, operands); DONE;")
(set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncdfdi2"
- [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
- (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
- "TARGET_FP"
- "")
+ [(set (match_operand:DI 0 "reg_no_subreg_operand")
+ (fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
+ "TARGET_FP")
(define_expand "fixuns_truncdfdi2"
- [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
- (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
- "TARGET_FP"
- "")
+ [(set (match_operand:DI 0 "reg_no_subreg_operand")
+ (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))]
+ "TARGET_FP")
;; Likewise between SFmode and SImode.
[(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
(set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
(set (match_dup 5) (match_dup 3))]
-{
- operands[5] = adjust_address (operands[0], SFmode, 0);
-}
+ "operands[5] = adjust_address (operands[0], SFmode, 0);"
[(set_attr "type" "fadd")
(set_attr "trap" "yes")])
(set_attr "trap_suffix" "v_sv_svi")])
(define_expand "fix_truncsfdi2"
- [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
- (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
- "TARGET_FP"
- "")
+ [(set (match_operand:DI 0 "reg_no_subreg_operand")
+ (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
+ "TARGET_FP")
(define_expand "fixuns_truncsfdi2"
- [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
+ [(set (match_operand:DI 0 "reg_no_subreg_operand")
(unsigned_fix:DI
- (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
- "TARGET_FP"
- "")
+ (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))]
+ "TARGET_FP")
(define_expand "fix_trunctfdi2"
- [(use (match_operand:DI 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))]
+ [(use (match_operand:DI 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FIX, operands); DONE;")
(define_expand "fixuns_trunctfdi2"
- [(use (match_operand:DI 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))]
+ [(use (match_operand:DI 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
[(set (match_dup 3) (match_dup 1))
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
(set (match_dup 0) (float:SF (match_dup 2)))]
-{
- operands[1] = adjust_address (operands[1], SFmode, 0);
-})
+ "operands[1] = adjust_address (operands[1], SFmode, 0);")
(define_insn_and_split "*floatsisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
[(set (match_dup 3) (match_dup 1))
(set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
(set (match_dup 0) (float:DF (match_dup 2)))]
-{
- operands[1] = adjust_address (operands[1], SFmode, 0);
-})
+ "operands[1] = adjust_address (operands[1], SFmode, 0);")
(define_insn_and_split "*floatsidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
})
(define_expand "floatditf2"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:DI 1 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:DI 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
(define_expand "floatunsdisf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))]
+ [(use (match_operand:SF 0 "register_operand"))
+ (use (match_operand:DI 1 "register_operand"))]
"TARGET_FP"
"alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:DI 1 "register_operand" ""))]
+ [(use (match_operand:DF 0 "register_operand"))
+ (use (match_operand:DI 1 "register_operand"))]
"TARGET_FP"
"alpha_emit_floatuns (operands); DONE;")
(define_expand "floatunsditf2"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:DI 1 "general_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:DI 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
(define_expand "extendsfdf2"
- [(set (match_operand:DF 0 "register_operand" "")
- (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
+ [(set (match_operand:DF 0 "register_operand")
+ (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))]
"TARGET_FP"
{
if (alpha_fptm >= ALPHA_FPTM_SU)
;; from doing something silly. When optimizing we'll put things back
;; together anyway.
(define_expand "extendsftf2"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:SF 1 "register_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:SF 1 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
{
rtx tmp = gen_reg_rtx (DFmode);
})
(define_expand "extenddftf2"
- [(use (match_operand:TF 0 "register_operand" ""))
- (use (match_operand:DF 1 "register_operand" ""))]
+ [(use (match_operand:TF 0 "register_operand"))
+ (use (match_operand:DF 1 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
(set_attr "trap_suffix" "u_su_sui")])
(define_expand "trunctfdf2"
- [(use (match_operand:DF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))]
+ [(use (match_operand:DF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
"alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
(define_expand "trunctfsf2"
- [(use (match_operand:SF 0 "register_operand" ""))
- (use (match_operand:TF 1 "general_operand" ""))]
+ [(use (match_operand:SF 0 "register_operand"))
+ (use (match_operand:TF 1 "general_operand"))]
"TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
{
rtx tmpf, sticky, arg, lo, hi;
;; For ABS, we have two choices, depending on whether the input and output
;; registers are the same or not.
(define_expand "absdi2"
- [(set (match_operand:DI 0 "register_operand" "")
- (abs:DI (match_operand:DI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (abs:DI (match_operand:DI 1 "register_operand")))]
""
{
if (rtx_equal_p (operands[0], operands[1]))
})
(define_expand "absdi2_same"
- [(set (match_operand:DI 1 "register_operand" "")
- (neg:DI (match_operand:DI 0 "register_operand" "")))
+ [(set (match_operand:DI 1 "register_operand")
+ (neg:DI (match_operand:DI 0 "register_operand")))
(set (match_dup 0)
(if_then_else:DI (ge (match_dup 0) (const_int 0))
(match_dup 0)
- (match_dup 1)))]
- ""
- "")
+ (match_dup 1)))])
(define_expand "absdi2_diff"
- [(set (match_operand:DI 0 "register_operand" "")
- (neg:DI (match_operand:DI 1 "register_operand" "")))
+ [(set (match_operand:DI 0 "register_operand")
+ (neg:DI (match_operand:DI 1 "register_operand")))
(set (match_dup 0)
(if_then_else:DI (lt (match_dup 1) (const_int 0))
(match_dup 0)
- (match_dup 1)))]
- ""
- "")
+ (match_dup 1)))])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(abs:DI (match_dup 0)))
- (clobber (match_operand:DI 1 "register_operand" ""))]
+ (clobber (match_operand:DI 1 "register_operand"))]
""
[(set (match_dup 1) (neg:DI (match_dup 0)))
(set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
- (match_dup 0) (match_dup 1)))]
- "")
+ (match_dup 0) (match_dup 1)))])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (abs:DI (match_operand:DI 1 "register_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (abs:DI (match_operand:DI 1 "register_operand")))]
"! rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 0) (neg:DI (match_dup 1)))
(set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
- (match_dup 0) (match_dup 1)))]
- "")
+ (match_dup 0) (match_dup 1)))])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(neg:DI (abs:DI (match_dup 0))))
- (clobber (match_operand:DI 1 "register_operand" ""))]
+ (clobber (match_operand:DI 1 "register_operand"))]
""
[(set (match_dup 1) (neg:DI (match_dup 0)))
(set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
- (match_dup 0) (match_dup 1)))]
- "")
+ (match_dup 0) (match_dup 1)))])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
+ [(set (match_operand:DI 0 "register_operand")
+ (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))]
"! rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 0) (neg:DI (match_dup 1)))
(set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
- (match_dup 0) (match_dup 1)))]
- "")
+ (match_dup 0) (match_dup 1)))])
(define_insn "<code><mode>3"
[(set (match_operand:I12MODE 0 "register_operand" "=r")
(define_expand "smaxdi3"
[(set (match_dup 3)
- (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
+ (le:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- { operands[3] = gen_reg_rtx (DImode); })
+ "operands[3] = gen_reg_rtx (DImode);")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (clobber (match_operand:DI 3 "register_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (smax:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx"
[(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
- (match_dup 1) (match_dup 2)))]
- "")
+ (match_dup 1) (match_dup 2)))])
(define_insn "*smax_const0"
[(set (match_operand:DI 0 "register_operand" "=r")
(define_expand "smindi3"
[(set (match_dup 3)
- (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
+ (lt:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
- { operands[3] = gen_reg_rtx (DImode); })
+ "operands[3] = gen_reg_rtx (DImode);")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (clobber (match_operand:DI 3 "register_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (smin:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx"
[(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
- (match_dup 1) (match_dup 2)))]
- "")
+ (match_dup 1) (match_dup 2)))])
(define_insn "*smin_const0"
[(set (match_operand:DI 0 "register_operand" "=r")
(define_expand "umaxdi3"
[(set (match_dup 3)
- (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
+ (leu:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (eq (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
"operands[3] = gen_reg_rtx (DImode);")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (clobber (match_operand:DI 3 "register_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (umax:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx"
[(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
- (match_dup 1) (match_dup 2)))]
- "")
+ (match_dup 1) (match_dup 2)))])
(define_expand "umindi3"
[(set (match_dup 3)
- (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (set (match_operand:DI 0 "register_operand" "")
+ (ltu:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (set (match_operand:DI 0 "register_operand")
(if_then_else:DI (ne (match_dup 3) (const_int 0))
(match_dup 1) (match_dup 2)))]
""
"operands[3] = gen_reg_rtx (DImode);")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")))
- (clobber (match_operand:DI 3 "register_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (umin:DI (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")))
+ (clobber (match_operand:DI 3 "register_operand"))]
"operands[2] != const0_rtx"
[(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
- (match_dup 1) (match_dup 2)))]
- "")
+ (match_dup 1) (match_dup 2)))])
(define_insn "*bcc_normal"
[(set (pc)
(match_operator 1 "signed_comparison_operator"
[(match_operand:DI 2 "reg_or_0_operand" "rJ")
(const_int 0)])
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
""
"b%C1 %r2,%0"
(const_int 0)])
(pc)
- (label_ref (match_operand 0 "" ""))))]
+ (label_ref (match_operand 0))))]
""
"b%c1 %2,%0"
[(set_attr "type" "ibr")])
(const_int 1)
(const_int 0))
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
""
"blbs %r1,%0"
(const_int 1)
(const_int 0))
(const_int 0))
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
""
"blbc %r1,%0"
[(set (pc)
(if_then_else
(match_operator 1 "comparison_operator"
- [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
- (const_int 1)
- (match_operand:DI 3 "const_int_operand" ""))
- (const_int 0)])
- (label_ref (match_operand 0 "" ""))
+ [(zero_extract:DI (match_operand:DI 2 "register_operand")
+ (const_int 1)
+ (match_operand:DI 3 "const_int_operand"))
+ (const_int 0)])
+ (label_ref (match_operand 0))
(pc)))
- (clobber (match_operand:DI 4 "register_operand" ""))])]
+ (clobber (match_operand:DI 4 "register_operand"))])]
"INTVAL (operands[3]) != 0"
[(set (match_dup 4)
(lshiftrt:DI (match_dup 2) (match_dup 3)))
(const_int 0)])
(label_ref (match_dup 0))
(pc)))]
- "")
+ )
\f
;; The following are the corresponding floating-point insns. Recall
;; we need to have variants that expand the arguments from SFmode
(define_expand "smaxdf3"
[(set (match_dup 3)
- (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
- (match_operand:DF 2 "reg_or_0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "")
+ (le:DF (match_operand:DF 1 "reg_or_0_operand")
+ (match_operand:DF 2 "reg_or_0_operand")))
+ (set (match_operand:DF 0 "register_operand")
(if_then_else:DF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
"TARGET_FP"
(define_expand "smindf3"
[(set (match_dup 3)
- (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
- (match_operand:DF 2 "reg_or_0_operand" "")))
- (set (match_operand:DF 0 "register_operand" "")
+ (lt:DF (match_operand:DF 1 "reg_or_0_operand")
+ (match_operand:DF 2 "reg_or_0_operand")))
+ (set (match_operand:DF 0 "register_operand")
(if_then_else:DF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
"TARGET_FP"
(define_expand "smaxsf3"
[(set (match_dup 3)
- (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
- (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
- (set (match_operand:SF 0 "register_operand" "")
+ (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
+ (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
+ (set (match_operand:SF 0 "register_operand")
(if_then_else:SF (eq (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
(define_expand "sminsf3"
[(set (match_dup 3)
- (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
- (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
- (set (match_operand:SF 0 "register_operand" "")
+ (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))
+ (float_extend:DF (match_operand:SF 2 "reg_or_0_operand"))))
+ (set (match_operand:SF 0 "register_operand")
(if_then_else:SF (ne (match_dup 3) (match_dup 4))
(match_dup 1) (match_dup 2)))]
"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
(match_operator 1 "signed_comparison_operator"
[(match_operand:DF 2 "reg_or_0_operand" "fG")
(match_operand:DF 3 "const0_operand" "G")])
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
"TARGET_FP"
"fb%C1 %R2,%0"
[(float_extend:DF
(match_operand:SF 2 "reg_or_0_operand" "fG"))
(match_operand:DF 3 "const0_operand" "G")])
- (label_ref (match_operand 0 "" ""))
+ (label_ref (match_operand 0))
(pc)))]
"TARGET_FP"
"fb%C1 %R2,%0"
(define_expand "cbranchdf4"
[(use (match_operator 0 "alpha_cbranch_operator"
- [(match_operand:DF 1 "reg_or_0_operand" "")
- (match_operand:DF 2 "reg_or_0_operand" "")]))
- (use (match_operand 3 ""))]
+ [(match_operand:DF 1 "reg_or_0_operand")
+ (match_operand:DF 2 "reg_or_0_operand")]))
+ (use (match_operand 3))]
"TARGET_FP"
- { alpha_emit_conditional_branch (operands, DFmode); DONE; })
+ "alpha_emit_conditional_branch (operands, DFmode); DONE;")
(define_expand "cbranchtf4"
[(use (match_operator 0 "alpha_cbranch_operator"
[(match_operand:TF 1 "general_operand")
(match_operand:TF 2 "general_operand")]))
- (use (match_operand 3 ""))]
+ (use (match_operand 3))]
"TARGET_HAS_XFLOATING_LIBS"
- { alpha_emit_conditional_branch (operands, TFmode); DONE; })
+ "alpha_emit_conditional_branch (operands, TFmode); DONE;")
(define_expand "cbranchdi4"
[(use (match_operator 0 "alpha_cbranch_operator"
[(match_operand:DI 1 "some_operand")
(match_operand:DI 2 "some_operand")]))
- (use (match_operand 3 ""))]
+ (use (match_operand 3))]
""
- { alpha_emit_conditional_branch (operands, DImode); DONE; })
+ "alpha_emit_conditional_branch (operands, DImode); DONE;")
(define_expand "cstoredf4"
[(use (match_operator:DI 1 "alpha_cbranch_operator"
(match_operand:DF 3 "reg_or_0_operand")]))
(clobber (match_operand:DI 0 "register_operand"))]
"TARGET_FP"
- { if (!alpha_emit_setcc (operands, DFmode)) FAIL; else DONE; })
+{
+ if (alpha_emit_setcc (operands, DFmode))
+ DONE;
+ else
+ FAIL;
+})
(define_expand "cstoretf4"
[(use (match_operator:DI 1 "alpha_cbranch_operator"
(match_operand:TF 3 "general_operand")]))
(clobber (match_operand:DI 0 "register_operand"))]
"TARGET_HAS_XFLOATING_LIBS"
- { if (!alpha_emit_setcc (operands, TFmode)) FAIL; else DONE; })
+{
+ if (alpha_emit_setcc (operands, TFmode))
+ DONE;
+ else
+ FAIL;
+})
(define_expand "cstoredi4"
[(use (match_operator:DI 1 "alpha_cbranch_operator"
(match_operand:DI 3 "some_operand")]))
(clobber (match_operand:DI 0 "register_operand"))]
""
- { if (!alpha_emit_setcc (operands, DImode)) FAIL; else DONE; })
+{
+ if (alpha_emit_setcc (operands, DImode))
+ DONE;
+ else
+ FAIL;
+})
\f
;; These are the main define_expand's used to make conditional moves.
(define_expand "mov<mode>cc"
- [(set (match_operand:I48MODE 0 "register_operand" "")
+ [(set (match_operand:I48MODE 0 "register_operand")
(if_then_else:I48MODE
- (match_operand 1 "comparison_operator" "")
- (match_operand:I48MODE 2 "reg_or_8bit_operand" "")
- (match_operand:I48MODE 3 "reg_or_8bit_operand" "")))]
+ (match_operand 1 "comparison_operator")
+ (match_operand:I48MODE 2 "reg_or_8bit_operand")
+ (match_operand:I48MODE 3 "reg_or_8bit_operand")))]
""
{
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
})
(define_expand "mov<mode>cc"
- [(set (match_operand:FMODE 0 "register_operand" "")
+ [(set (match_operand:FMODE 0 "register_operand")
(if_then_else:FMODE
- (match_operand 1 "comparison_operator" "")
- (match_operand:FMODE 2 "reg_or_8bit_operand" "")
- (match_operand:FMODE 3 "reg_or_8bit_operand" "")))]
+ (match_operand 1 "comparison_operator")
+ (match_operand:FMODE 2 "reg_or_8bit_operand")
+ (match_operand:FMODE 3 "reg_or_8bit_operand")))]
""
{
operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode);
;; operation could have been generated.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(if_then_else:DI
(match_operator 1 "comparison_operator"
- [(match_operand:DI 2 "reg_or_0_operand" "")
- (match_operand:DI 3 "reg_or_cint_operand" "")])
- (match_operand:DI 4 "reg_or_cint_operand" "")
- (match_operand:DI 5 "reg_or_cint_operand" "")))
- (clobber (match_operand:DI 6 "register_operand" ""))]
+ [(match_operand:DI 2 "reg_or_0_operand")
+ (match_operand:DI 3 "reg_or_cint_operand")])
+ (match_operand:DI 4 "reg_or_cint_operand")
+ (match_operand:DI 5 "reg_or_cint_operand")))
+ (clobber (match_operand:DI 6 "register_operand"))]
"operands[3] != const0_rtx"
[(set (match_dup 6) (match_dup 7))
(set (match_dup 0)
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(if_then_else:DI
(match_operator 1 "comparison_operator"
- [(match_operand:SI 2 "reg_or_0_operand" "")
- (match_operand:SI 3 "reg_or_cint_operand" "")])
- (match_operand:DI 4 "reg_or_8bit_operand" "")
- (match_operand:DI 5 "reg_or_8bit_operand" "")))
- (clobber (match_operand:DI 6 "register_operand" ""))]
+ [(match_operand:SI 2 "reg_or_0_operand")
+ (match_operand:SI 3 "reg_or_cint_operand")])
+ (match_operand:DI 4 "reg_or_8bit_operand")
+ (match_operand:DI 5 "reg_or_8bit_operand")))
+ (clobber (match_operand:DI 6 "register_operand"))]
"operands[3] != const0_rtx
&& (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
[(set (match_dup 6) (match_dup 7))
;; Prefer to use cmp and arithmetic when possible instead of a cmove.
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "signed_comparison_operator"
- [(match_operand:DI 2 "reg_or_0_operand" "")
+ [(match_operand:DI 2 "reg_or_0_operand")
(const_int 0)])
- (match_operand 3 "const_int_operand" "")
- (match_operand 4 "const_int_operand" "")))]
+ (match_operand 3 "const_int_operand")
+ (match_operand 4 "const_int_operand")))]
""
[(const_int 0)]
{
;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
;; Oh well, we match it in movcc, so it must be partially our fault.
(define_split
- [(set (match_operand 0 "register_operand" "")
+ [(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "signed_comparison_operator"
[(const_int 0)
- (match_operand:DI 2 "reg_or_0_operand" "")])
- (match_operand 3 "const_int_operand" "")
- (match_operand 4 "const_int_operand" "")))]
+ (match_operand:DI 2 "reg_or_0_operand")])
+ (match_operand 3 "const_int_operand")
+ (match_operand 4 "const_int_operand")))]
""
[(const_int 0)]
{
;; work differently, so we have different patterns for each.
(define_expand "call"
- [(use (match_operand:DI 0 "" ""))
- (use (match_operand 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))]
+ [(use (match_operand:DI 0))
+ (use (match_operand 1))
+ (use (match_operand 2))
+ (use (match_operand 3))]
""
{
if (TARGET_ABI_OPEN_VMS)
})
(define_expand "sibcall"
- [(parallel [(call (mem:DI (match_operand 0 "" ""))
- (match_operand 1 "" ""))
+ [(parallel [(call (mem:DI (match_operand 0))
+ (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
})
(define_expand "call_osf"
- [(parallel [(call (mem:DI (match_operand 0 "" ""))
- (match_operand 1 "" ""))
+ [(parallel [(call (mem:DI (match_operand 0))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
""
;; op 1: next_arg_reg (argument information value for R25)
;;
(define_expand "call_vms"
- [(parallel [(call (mem:DI (match_operand 0 "" ""))
- (match_operand 1 "" ""))
+ [(parallel [(call (mem:DI (match_operand 0))
+ (match_operand 1))
(use (match_dup 2))
(use (reg:DI 25))
(use (reg:DI 26))
operands[0], 8)));
operands[2] = operands[0];
}
-
})
(define_expand "call_value"
- [(use (match_operand 0 "" ""))
- (use (match_operand:DI 1 "" ""))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "" ""))
- (use (match_operand 4 "" ""))]
+ [(use (match_operand 0))
+ (use (match_operand:DI 1))
+ (use (match_operand 2))
+ (use (match_operand 3))
+ (use (match_operand 4))]
""
{
if (TARGET_ABI_OPEN_VMS)
})
(define_expand "sibcall_value"
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand 1 "" ""))
- (match_operand 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (mem:DI (match_operand 1))
+ (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
"TARGET_ABI_OSF"
{
})
(define_expand "call_value_osf"
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand 1 "" ""))
- (match_operand 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (mem:DI (match_operand 1))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
""
})
(define_expand "call_value_vms"
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "" ""))
- (match_operand 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1))
+ (match_operand 2)))
(use (match_dup 3))
(use (reg:DI 25))
(use (reg:DI 26))
(define_insn "*call_osf_1_er_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
(define_insn "*call_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
;; We must use peep2 instead of a split because we need accurate life
;; information for $gp. Consider the case of { bar(); while (1); }.
(define_peephole2
- [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
- (match_operand 1 "" ""))
+ [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
})
(define_peephole2
- [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
- (match_operand 1 "" ""))
+ [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand"))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
(define_insn "*call_osf_2_er_nogp"
[(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (reg:DI 29))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "const_int_operand" ""))
+ (use (match_operand 2))
+ (use (match_operand 3 "const_int_operand"))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%0),%2%J3"
(define_insn "*call_osf_2_er"
[(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(set (reg:DI 29)
- (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand" "")]
+ (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")]
UNSPEC_LDGP1))
- (use (match_operand 2 "" ""))
- (use (match_operand 3 "const_int_operand" ""))
+ (use (match_operand 2))
+ (use (match_operand 3 "const_int_operand"))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4"
(define_insn "*call_osf_1_noreturn"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
(define_insn "*call_osf_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
(define_insn "*sibcall_osf_1_er"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
;; doesn't do what we want.
(define_insn "*sibcall_osf_1"
[(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
; Please do not molest.
(define_insn "*call_vms_1"
[(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
- (match_operand 1 "" ""))
+ (match_operand 1))
(use (match_operand:DI 2 "nonmemory_operand" "r,n"))
(use (reg:DI 25))
(use (reg:DI 26))
;; Call subroutine returning any type.
(define_expand "untyped_call"
- [(parallel [(call (match_operand 0 "" "")
+ [(parallel [(call (match_operand 0)
(const_int 0))
- (match_operand 1 "" "")
- (match_operand 2 "" "")])]
+ (match_operand 1)
+ (match_operand 2)])]
""
{
int i;
(define_insn "jump"
[(set (pc)
- (label_ref (match_operand 0 "" "")))]
+ (label_ref (match_operand 0)))]
""
"br $31,%l0"
[(set_attr "type" "ibr")])
(define_expand "return"
[(return)]
- "direct_return ()"
- "")
+ "direct_return ()")
(define_insn "*return_internal"
[(return)]
(define_expand "tablejump"
[(parallel [(set (pc)
- (match_operand 0 "register_operand" ""))
- (use (label_ref:DI (match_operand 1 "" "")))])]
+ (match_operand 0 "register_operand"))
+ (use (label_ref:DI (match_operand 1)))])]
""
{
if (TARGET_ABI_OSF)
(define_insn "*tablejump_internal"
[(set (pc)
(match_operand:DI 0 "register_operand" "r"))
- (use (label_ref (match_operand 1 "" "")))]
+ (use (label_ref (match_operand 1)))]
""
"jmp $31,(%0),0"
[(set_attr "type" "ibr")])
[(set_attr "type" "callpal")])
(define_expand "clear_cache"
- [(match_operand:DI 0 "") ; region start
- (match_operand:DI 1 "")] ; region end
+ [(match_operand:DI 0) ; region start
+ (match_operand:DI 1)] ; region end
""
{
emit_insn (gen_imb ());
;; not much point in creating an R16_REG register class.
(define_expand "set_thread_pointerdi"
- [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
+ [(set (reg:DI 16) (match_operand:DI 0 "input_operand"))
(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
- "TARGET_ABI_OSF"
- "")
+ "TARGET_ABI_OSF")
(define_insn "*set_tp"
[(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
;; Special builtins for establishing and reverting VMS condition handlers.
(define_expand "builtin_establish_vms_condition_handler"
- [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))
- (use (match_operand:DI 1 "address_operand" ""))]
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))
+ (use (match_operand:DI 1 "address_operand"))]
"TARGET_ABI_OPEN_VMS"
{
alpha_expand_builtin_establish_vms_condition_handler (operands[0],
})
(define_expand "builtin_revert_vms_condition_handler"
- [(set (reg:DI 0) (match_operand:DI 0 "register_operand" ""))]
+ [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))]
"TARGET_ABI_OPEN_VMS"
-{
- alpha_expand_builtin_revert_vms_condition_handler (operands[0]);
-})
+ "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);")
\f
;; Finally, we have the basic data motion insns. The byte and word insns
;; are done via define_expand. Start with the floating-point insns, since
;; they are simpler.
(define_expand "movsf"
- [(set (match_operand:SF 0 "nonimmediate_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
+ [(set (match_operand:SF 0 "nonimmediate_operand")
+ (match_operand:SF 1 "general_operand"))]
""
{
if (MEM_P (operands[0])
(set_attr "isa" "*,*,*,*,*,*,fix,fix")])
(define_expand "movdf"
- [(set (match_operand:DF 0 "nonimmediate_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+ [(set (match_operand:DF 0 "nonimmediate_operand")
+ (match_operand:DF 1 "general_operand"))]
""
{
if (MEM_P (operands[0])
;; ??? Is this still true now that we have the lower-subreg pass?
(define_expand "movtf"
- [(set (match_operand:TF 0 "nonimmediate_operand" "")
- (match_operand:TF 1 "general_operand" ""))]
+ [(set (match_operand:TF 0 "nonimmediate_operand")
+ (match_operand:TF 1 "general_operand"))]
""
{
if (MEM_P (operands[0])
"reload_completed"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 1) (match_dup 3))]
-{
- alpha_split_tmode_pair (operands, TFmode, true);
-})
+ "alpha_split_tmode_pair (operands, TFmode, true);")
;; We do two major things here: handle mem->mem and construct long
;; constants.
(define_expand "movsi"
- [(set (match_operand:SI 0 "nonimmediate_operand" "")
- (match_operand:SI 1 "general_operand" ""))]
+ [(set (match_operand:SI 0 "nonimmediate_operand")
+ (match_operand:SI 1 "general_operand"))]
""
{
if (alpha_expand_mov (SImode, operands))
;; sequence.
(define_split
- [(set (match_operand:SI 0 "register_operand" "")
- (match_operand:SI 1 "non_add_const_operand" ""))]
+ [(set (match_operand:SI 0 "register_operand")
+ (match_operand:SI 1 "non_add_const_operand"))]
""
[(const_int 0)]
{
(define_insn "*movdi_er_low_l"
[(set (match_operand:DI 0 "register_operand" "=r")
(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "local_symbolic_operand" "")))]
+ (match_operand:DI 2 "local_symbolic_operand")))]
"TARGET_EXPLICIT_RELOCS"
{
if (true_regnum (operands[1]) == 29)
[(set_attr "usegp" "yes")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "small_symbolic_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "small_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0)
(lo_sum:DI (match_dup 2) (match_dup 1)))]
"operands[2] = pic_offset_table_rtx;")
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "local_symbolic_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "local_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0)
(plus:DI (match_dup 2) (high:DI (match_dup 1))))
"operands[2] = pic_offset_table_rtx;")
(define_split
- [(match_operand 0 "some_small_symbolic_operand" "")]
+ [(match_operand 0 "some_small_symbolic_operand")]
""
[(match_dup 0)]
"operands[0] = split_small_symbolic_operand (operands[0]);")
(define_insn "movdi_er_high_g"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "symbolic_operand" "")
- (match_operand 3 "const_int_operand" "")]
+ (match_operand:DI 2 "symbolic_operand")
+ (match_operand 3 "const_int_operand")]
UNSPEC_LITERAL))]
"TARGET_EXPLICIT_RELOCS"
{
[(set_attr "type" "ldsym")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "global_symbolic_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "global_symbolic_operand"))]
"TARGET_EXPLICIT_RELOCS && reload_completed"
[(set (match_dup 0)
(unspec:DI [(match_dup 2)
(define_insn "movdi_er_tlsgd"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "symbolic_operand" "")
- (match_operand 3 "const_int_operand" "")]
+ (match_operand:DI 2 "symbolic_operand")
+ (match_operand 3 "const_int_operand")]
UNSPEC_TLSGD))]
"HAVE_AS_TLS"
{
(define_insn "movdi_er_tlsldm"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPEC_TLSLDM))]
"HAVE_AS_TLS"
{
(define_insn "*movdi_er_gotdtp"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "symbolic_operand" "")]
+ (match_operand:DI 2 "symbolic_operand")]
UNSPEC_DTPREL))]
"HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gotdtprel"
(set_attr "usegp" "yes")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "gotdtp_symbolic_operand"))]
"HAVE_AS_TLS && reload_completed"
[(set (match_dup 0)
(unspec:DI [(match_dup 2)
(define_insn "*movdi_er_gottp"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "symbolic_operand" "")]
+ (match_operand:DI 2 "symbolic_operand")]
UNSPEC_TPREL))]
"HAVE_AS_TLS"
"ldq %0,%2(%1)\t\t!gottprel"
(set_attr "usegp" "yes")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "gottp_symbolic_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "gottp_symbolic_operand"))]
"HAVE_AS_TLS && reload_completed"
[(set (match_dup 0)
(unspec:DI [(match_dup 2)
;; memory, and construct long 32-bit constants.
(define_expand "movdi"
- [(set (match_operand:DI 0 "nonimmediate_operand" "")
- (match_operand:DI 1 "general_operand" ""))]
+ [(set (match_operand:DI 0 "nonimmediate_operand")
+ (match_operand:DI 1 "general_operand"))]
""
{
if (alpha_expand_mov (DImode, operands))
;; sequence.
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "non_add_const_operand" ""))]
+ [(set (match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "non_add_const_operand"))]
""
[(const_int 0)]
{
"reload_completed"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 1) (match_dup 3))]
-{
- alpha_split_tmode_pair (operands, TImode, true);
-})
+ "alpha_split_tmode_pair (operands, TImode, true);")
(define_expand "movti"
- [(set (match_operand:TI 0 "nonimmediate_operand" "")
- (match_operand:TI 1 "general_operand" ""))]
+ [(set (match_operand:TI 0 "nonimmediate_operand")
+ (match_operand:TI 1 "general_operand"))]
""
{
if (MEM_P (operands[0])
;; same register. It is allowed to conflict with operand 1 as well.
(define_expand "aligned_loadqi"
- [(set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 1 "memory_operand" ""))
- (set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:SI 3 "register_operand")
+ (match_operand:SI 1 "memory_operand"))
+ (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 8)
- (match_operand:DI 2 "const_int_operand" "")))]
-
- ""
- "")
+ (match_operand:DI 2 "const_int_operand")))])
(define_expand "aligned_loadhi"
- [(set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 1 "memory_operand" ""))
- (set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:SI 3 "register_operand")
+ (match_operand:SI 1 "memory_operand"))
+ (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (subreg:DI (match_dup 3) 0)
(const_int 16)
- (match_operand:DI 2 "const_int_operand" "")))]
-
- ""
- "")
+ (match_operand:DI 2 "const_int_operand")))])
;; Similar for unaligned loads, where we use the sequence from the
;; Alpha Architecture manual. We have to distinguish between little-endian
;; operand 3 can overlap the input and output registers.
(define_expand "unaligned_loadqi"
- [(set (match_operand:DI 2 "register_operand" "")
- (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
+ [(set (match_operand:DI 2 "register_operand")
+ (mem:DI (and:DI (match_operand:DI 1 "address_operand")
(const_int -8))))
- (set (match_operand:DI 3 "register_operand" "")
+ (set (match_operand:DI 3 "register_operand")
(match_dup 1))
- (set (match_operand:DI 0 "register_operand" "")
+ (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_dup 2)
(const_int 8)
- (ashift:DI (match_dup 3) (const_int 3))))]
- ""
- "")
+ (ashift:DI (match_dup 3) (const_int 3))))])
(define_expand "unaligned_loadhi"
- [(set (match_operand:DI 2 "register_operand" "")
- (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
+ [(set (match_operand:DI 2 "register_operand")
+ (mem:DI (and:DI (match_operand:DI 1 "address_operand")
(const_int -8))))
- (set (match_operand:DI 3 "register_operand" "")
+ (set (match_operand:DI 3 "register_operand")
(match_dup 1))
- (set (match_operand:DI 0 "register_operand" "")
+ (set (match_operand:DI 0 "register_operand")
(zero_extract:DI (match_dup 2)
(const_int 16)
- (ashift:DI (match_dup 3) (const_int 3))))]
- ""
- "")
+ (ashift:DI (match_dup 3) (const_int 3))))])
;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
;; aligned SImode MEM. Operand 1 is the register containing the
;; the value should be placed. Operands 3 and 4 are SImode temporaries.
(define_expand "aligned_store"
- [(set (match_operand:SI 3 "register_operand" "")
- (match_operand:SI 0 "memory_operand" ""))
+ [(set (match_operand:SI 3 "register_operand")
+ (match_operand:SI 0 "memory_operand"))
(set (subreg:DI (match_dup 3) 0)
(and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
- (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
- (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
- (match_operand:DI 2 "const_int_operand" "")))
+ (set (subreg:DI (match_operand:SI 4 "register_operand") 0)
+ (ashift:DI (zero_extend:DI (match_operand 1 "register_operand"))
+ (match_operand:DI 2 "const_int_operand")))
(set (subreg:DI (match_dup 4) 0)
(ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
(set (match_dup 0) (match_dup 4))]
;; operand 2 can be that register.
(define_expand "unaligned_store<mode>"
- [(set (match_operand:DI 3 "register_operand" "")
- (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
+ [(set (match_operand:DI 3 "register_operand")
+ (mem:DI (and:DI (match_operand:DI 0 "address_operand")
(const_int -8))))
- (set (match_operand:DI 2 "register_operand" "")
+ (set (match_operand:DI 2 "register_operand")
(match_dup 0))
(set (match_dup 3)
(and:DI (not:DI (ashift:DI (match_dup 5)
(ashift:DI (match_dup 2) (const_int 3))))
(match_dup 3)))
- (set (match_operand:DI 4 "register_operand" "")
+ (set (match_operand:DI 4 "register_operand")
(ashift:DI (zero_extend:DI
- (match_operand:I12MODE 1 "register_operand" ""))
+ (match_operand:I12MODE 1 "register_operand"))
(ashift:DI (match_dup 2) (const_int 3))))
(set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
(set (mem:DI (and:DI (match_dup 0) (const_int -8)))
;; registers for reload.
(define_expand "mov<mode>"
- [(set (match_operand:I12MODE 0 "nonimmediate_operand" "")
- (match_operand:I12MODE 1 "general_operand" ""))]
+ [(set (match_operand:I12MODE 0 "nonimmediate_operand")
+ (match_operand:I12MODE 1 "general_operand"))]
""
{
if (TARGET_BWX
;; We need to hook into the extra support that we have for HImode
;; reloads when BWX insns are not available.
(define_expand "movcqi"
- [(set (match_operand:CQI 0 "nonimmediate_operand" "")
- (match_operand:CQI 1 "general_operand" ""))]
+ [(set (match_operand:CQI 0 "nonimmediate_operand")
+ (match_operand:CQI 1 "general_operand"))]
"!TARGET_BWX"
{
if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT)
(define_mode_iterator VEC12 [V8QI V4HI])
(define_expand "mov<mode>"
- [(set (match_operand:VEC 0 "nonimmediate_operand" "")
- (match_operand:VEC 1 "general_operand" ""))]
+ [(set (match_operand:VEC 0 "nonimmediate_operand")
+ (match_operand:VEC 1 "general_operand"))]
""
{
if (alpha_expand_mov (<MODE>mode, operands))
})
(define_split
- [(set (match_operand:VEC 0 "register_operand" "")
- (match_operand:VEC 1 "non_zero_const_operand" ""))]
+ [(set (match_operand:VEC 0 "register_operand")
+ (match_operand:VEC 1 "non_zero_const_operand"))]
""
[(const_int 0)]
{
(define_expand "movmisalign<mode>"
- [(set (match_operand:VEC 0 "nonimmediate_operand" "")
- (match_operand:VEC 1 "general_operand" ""))]
+ [(set (match_operand:VEC 0 "nonimmediate_operand")
+ (match_operand:VEC 1 "general_operand"))]
""
{
alpha_expand_movmisalign (<MODE>mode, operands);
[(set_attr "type" "ilog")])
(define_expand "vec_shl_<mode>"
- [(set (match_operand:VEC 0 "register_operand" "")
- (ashift:DI (match_operand:VEC 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ [(set (match_operand:VEC 0 "register_operand")
+ (ashift:DI (match_operand:VEC 1 "register_operand")
+ (match_operand:DI 2 "reg_or_6bit_operand")))]
""
{
operands[0] = gen_lowpart (DImode, operands[0]);
})
(define_expand "vec_shr_<mode>"
- [(set (match_operand:VEC 0 "register_operand" "")
- (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ [(set (match_operand:VEC 0 "register_operand")
+ (lshiftrt:DI (match_operand:VEC 1 "register_operand")
+ (match_operand:DI 2 "reg_or_6bit_operand")))]
""
{
operands[0] = gen_lowpart (DImode, operands[0]);
;; Bit field extract patterns which use ext[wlq][lh]
(define_expand "extv"
- [(set (match_operand:DI 0 "register_operand" "")
- (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
- (match_operand:DI 2 "immediate_operand" "")
- (match_operand:DI 3 "immediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (sign_extract:DI (match_operand:QI 1 "memory_operand")
+ (match_operand:DI 2 "immediate_operand")
+ (match_operand:DI 3 "immediate_operand")))]
""
{
int ofs;
})
(define_expand "extzv"
- [(set (match_operand:DI 0 "register_operand" "")
- (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
- (match_operand:DI 2 "immediate_operand" "")
- (match_operand:DI 3 "immediate_operand" "")))]
+ [(set (match_operand:DI 0 "register_operand")
+ (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand")
+ (match_operand:DI 2 "immediate_operand")
+ (match_operand:DI 3 "immediate_operand")))]
""
{
/* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
})
(define_expand "insv"
- [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
- (match_operand:DI 1 "immediate_operand" "")
- (match_operand:DI 2 "immediate_operand" ""))
- (match_operand:DI 3 "register_operand" ""))]
+ [(set (zero_extract:DI (match_operand:QI 0 "memory_operand")
+ (match_operand:DI 1 "immediate_operand")
+ (match_operand:DI 2 "immediate_operand"))
+ (match_operand:DI 3 "register_operand"))]
""
{
int ofs;
;; Argument 3 is the alignment
(define_expand "movmemqi"
- [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:DI 2 "immediate_operand" ""))
- (use (match_operand:DI 3 "immediate_operand" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "memory_operand")
+ (match_operand:BLK 1 "memory_operand"))
+ (use (match_operand:DI 2 "immediate_operand"))
+ (use (match_operand:DI 3 "immediate_operand"))])]
""
{
if (alpha_expand_block_move (operands))
})
(define_expand "movmemdi"
- [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand:BLK 1 "memory_operand" ""))
- (use (match_operand:DI 2 "immediate_operand" ""))
- (use (match_operand:DI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand")
+ (match_operand:BLK 1 "memory_operand"))
+ (use (match_operand:DI 2 "immediate_operand"))
+ (use (match_operand:DI 3 "immediate_operand"))
(use (match_dup 4))
(clobber (reg:DI 25))
(clobber (reg:DI 16))
(clobber (reg:DI 26))
(clobber (reg:DI 27))])]
"TARGET_ABI_OPEN_VMS"
-{
- operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
-})
+ "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");")
(define_insn "*movmemdi_1"
[(set (match_operand:BLK 0 "memory_operand" "=m,=m")
(match_operand:BLK 1 "memory_operand" "m,m"))
(use (match_operand:DI 2 "nonmemory_operand" "r,i"))
- (use (match_operand:DI 3 "immediate_operand" ""))
+ (use (match_operand:DI 3 "immediate_operand"))
(use (match_operand:DI 4 "call_operand" "i,i"))
(clobber (reg:DI 25))
(clobber (reg:DI 16))
(set_attr "length" "28")])
(define_expand "setmemqi"
- [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand 2 "const_int_operand" ""))
- (use (match_operand:DI 1 "immediate_operand" ""))
- (use (match_operand:DI 3 "immediate_operand" ""))])]
+ [(parallel [(set (match_operand:BLK 0 "memory_operand")
+ (match_operand 2 "const_int_operand"))
+ (use (match_operand:DI 1 "immediate_operand"))
+ (use (match_operand:DI 3 "immediate_operand"))])]
""
{
/* If value to set is not zero, use the library routine. */
})
(define_expand "setmemdi"
- [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
- (match_operand 2 "const_int_operand" ""))
- (use (match_operand:DI 1 "immediate_operand" ""))
- (use (match_operand:DI 3 "immediate_operand" ""))
+ [(parallel [(set (match_operand:BLK 0 "memory_operand")
+ (match_operand 2 "const_int_operand"))
+ (use (match_operand:DI 1 "immediate_operand"))
+ (use (match_operand:DI 3 "immediate_operand"))
(use (match_dup 4))
(clobber (reg:DI 25))
(clobber (reg:DI 16))
[(set (match_operand:BLK 0 "memory_operand" "=m,=m")
(const_int 0))
(use (match_operand:DI 1 "nonmemory_operand" "r,i"))
- (use (match_operand:DI 2 "immediate_operand" ""))
+ (use (match_operand:DI 2 "immediate_operand"))
(use (match_operand:DI 3 "call_operand" "i,i"))
(clobber (reg:DI 25))
(clobber (reg:DI 16))
\f
;; Subroutine of stack space allocation. Perform a stack probe.
(define_expand "probe_stack"
- [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
+ [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))]
""
{
operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx,
(define_expand "allocate_stack"
[(set (reg:DI 30)
(plus:DI (reg:DI 30)
- (match_operand:DI 1 "reg_or_cint_operand" "")))
+ (match_operand:DI 1 "reg_or_cint_operand")))
(set (match_operand:DI 0 "register_operand" "=r")
(match_dup 2))]
""
(set_attr "type" "multi")])
(define_expand "prologue"
- [(clobber (const_int 0))]
+ [(const_int 0)]
""
{
alpha_expand_prologue ();
(define_insn "*ldgp_er_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPECV_LDGP1))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"ldah %0,0(%1)\t\t!gpdisp!%2"
(define_insn "*ldgp_er_2"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPEC_LDGP2))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"lda %0,0(%1)\t\t!gpdisp!%2"
(define_insn "*prologue_ldgp_er_2"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPECV_PLDGP2))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
(define_insn "*prologue_ldgp_1"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPECV_LDGP1))]
""
"ldgp %0,0(%1)\n$%~..ng:"
(define_insn "*prologue_ldgp_2"
[(set (match_operand:DI 0 "register_operand" "=r")
(unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
- (match_operand 2 "const_int_operand" "")]
+ (match_operand 2 "const_int_operand")]
UNSPECV_PLDGP2))]
""
- "")
+ )
;; The _mcount profiling hook has special calling conventions, and
;; does not clobber all the registers that a normal call would. So
(define_expand "epilogue"
[(return)]
""
-{
- alpha_expand_epilogue ();
-})
+ "alpha_expand_epilogue ();")
(define_expand "sibcall_epilogue"
[(return)]
[(set_attr "type" "ibr")])
(define_expand "builtin_setjmp_receiver"
- [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
- "TARGET_ABI_OSF"
- "")
+ [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)]
+ "TARGET_ABI_OSF")
(define_insn_and_split "*builtin_setjmp_receiver_1"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)]
"TARGET_ABI_OSF"
{
if (TARGET_EXPLICIT_RELOCS)
(set_attr "type" "multi")])
(define_insn "*builtin_setjmp_receiver_er_sl_1"
- [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
+ [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)]
"TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
"lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
(set (reg:DI 27) (mem:DI (reg:DI 29)))
(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
(use (reg:DI 27))]
- "TARGET_ABI_OPEN_VMS"
- "")
+ "TARGET_ABI_OPEN_VMS")
(define_insn "arg_home"
[(unspec [(const_int 0)] UNSPEC_ARG_HOME)
[(set_attr "type" "icmp")])
(define_expand "extbl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2]));
})
(define_expand "extwl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2]));
})
(define_expand "extll"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2]));
})
(define_expand "extql"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2]));
})
(define_expand "builtin_insbl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
operands[1] = gen_lowpart (QImode, operands[1]);
})
(define_expand "builtin_inswl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
operands[1] = gen_lowpart (HImode, operands[1]);
})
(define_expand "builtin_insll"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
operands[1] = gen_lowpart (SImode, operands[1]);
})
(define_expand "inswh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
})
(define_expand "inslh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
})
(define_expand "insqh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
})
(define_expand "mskbl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
rtx mask = GEN_INT (0xff);
})
(define_expand "mskwl"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
rtx mask = GEN_INT (0xffff);
})
(define_expand "mskll"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
rtx mask = immed_double_const (0xffffffff, 0, DImode);
})
(define_expand "mskql"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
rtx mask = constm1_rtx;
})
(define_expand "mskwh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
})
(define_expand "msklh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
})
(define_expand "mskqh"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "register_operand" "")
- (match_operand:DI 2 "reg_or_8bit_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "reg_or_8bit_operand")]
""
{
emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
})
(define_expand "builtin_zap"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI
- [(match_operand:DI 2 "reg_or_cint_operand" "")]
+ [(match_operand:DI 2 "reg_or_cint_operand")]
UNSPEC_ZAP)
- (match_operand:DI 1 "reg_or_cint_operand" "")))]
+ (match_operand:DI 1 "reg_or_cint_operand")))]
""
{
if (CONST_INT_P (operands[2]))
[(set_attr "type" "shift,shift,ilog,shift")])
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI
- [(match_operand:QI 2 "const_int_operand" "")]
+ [(match_operand:QI 2 "const_int_operand")]
UNSPEC_ZAP)
- (match_operand:DI 1 "const_int_operand" "")))]
+ (match_operand:DI 1 "const_int_operand")))]
""
[(const_int 0)]
{
})
(define_split
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI
- [(match_operand:QI 2 "const_int_operand" "")]
+ [(match_operand:QI 2 "const_int_operand")]
UNSPEC_ZAP)
- (match_operand:DI 1 "register_operand" "")))]
+ (match_operand:DI 1 "register_operand")))]
""
[(set (match_dup 0)
(and:DI (match_dup 1) (match_dup 2)))]
})
(define_expand "builtin_zapnot"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(and:DI (unspec:DI
- [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
+ [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))]
UNSPEC_ZAP)
- (match_operand:DI 1 "reg_or_cint_operand" "")))]
+ (match_operand:DI 1 "reg_or_cint_operand")))]
""
{
if (CONST_INT_P (operands[2]))
[(set_attr "type" "ilog")])
(define_expand "builtin_minub8"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
})
(define_expand "builtin_minsb8"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
})
(define_expand "builtin_minuw4"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
})
(define_expand "builtin_minsw4"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
})
(define_expand "builtin_maxub8"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
})
(define_expand "builtin_maxsb8"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
})
(define_expand "builtin_maxuw4"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
})
(define_expand "builtin_maxsw4"
- [(match_operand:DI 0 "register_operand" "")
- (match_operand:DI 1 "reg_or_0_operand" "")
- (match_operand:DI 2 "reg_or_0_operand" "")]
+ [(match_operand:DI 0 "register_operand")
+ (match_operand:DI 1 "reg_or_0_operand")
+ (match_operand:DI 2 "reg_or_0_operand")]
"TARGET_MAX"
{
alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
[(set_attr "type" "mvi")])
(define_expand "builtin_pklb"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(vec_concat:V8QI
(vec_concat:V4QI
- (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
+ (truncate:V2QI (match_operand:DI 1 "register_operand"))
(match_dup 2))
(match_dup 3)))]
"TARGET_MAX"
(vec_concat:V8QI
(vec_concat:V4QI
(truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
- (match_operand:V2QI 2 "const0_operand" ""))
- (match_operand:V4QI 3 "const0_operand" "")))]
+ (match_operand:V2QI 2 "const0_operand"))
+ (match_operand:V4QI 3 "const0_operand")))]
"TARGET_MAX"
"pklb %r1,%0"
[(set_attr "type" "mvi")])
(define_expand "builtin_pkwb"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(vec_concat:V8QI
- (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
+ (truncate:V4QI (match_operand:DI 1 "register_operand"))
(match_dup 2)))]
"TARGET_MAX"
{
[(set (match_operand:V8QI 0 "register_operand" "=r")
(vec_concat:V8QI
(truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
- (match_operand:V4QI 2 "const0_operand" "")))]
+ (match_operand:V4QI 2 "const0_operand")))]
"TARGET_MAX"
"pkwb %r1,%0"
[(set_attr "type" "mvi")])
(define_expand "builtin_unpkbl"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:V2SI
- (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
+ (vec_select:V2QI (match_operand:DI 1 "register_operand")
(parallel [(const_int 0) (const_int 1)]))))]
"TARGET_MAX"
{
[(set_attr "type" "mvi")])
(define_expand "builtin_unpkbw"
- [(set (match_operand:DI 0 "register_operand" "")
+ [(set (match_operand:DI 0 "register_operand")
(zero_extend:V4HI
- (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
+ (vec_select:V4QI (match_operand:DI 1 "register_operand")
(parallel [(const_int 0)
(const_int 1)
(const_int 2)
;; wildcard operand0 interferes with nice recognition.
(define_insn "*call_value_osf_1_er_noreturn"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
(set_attr "length" "*,*,8")])
(define_insn "*call_value_osf_1_er"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
;; We must use peep2 instead of a split because we need accurate life
;; information for $gp. Consider the case of { bar(); while (1); }.
(define_peephole2
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "call_operand" ""))
- (match_operand 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "call_operand"))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
})
(define_peephole2
- [(parallel [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "call_operand" ""))
- (match_operand 2 "" "")))
+ [(parallel [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "call_operand"))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))])]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
})
(define_insn "*call_value_osf_2_er_nogp"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "register_operand" "c"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (reg:DI 29))
- (use (match_operand 3 "" ""))
- (use (match_operand 4 "" ""))
+ (use (match_operand 3))
+ (use (match_operand 4))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%1),%3%J4"
[(set_attr "type" "jsr")])
(define_insn "*call_value_osf_2_er"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "register_operand" "c"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(set (reg:DI 29)
- (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand" "")]
+ (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")]
UNSPEC_LDGP1))
- (use (match_operand 3 "" ""))
- (use (match_operand 4 "" ""))
+ (use (match_operand 3))
+ (use (match_operand 4))
(clobber (reg:DI 26))]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5"
(set_attr "length" "8")])
(define_insn "*call_value_osf_1_noreturn"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
(set_attr "length" "*,*,8")])
(define_insn_and_split "call_value_osf_tlsgd"
- [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
+ [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
(const_int 0)))
- (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
+ (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL)
(use (reg:DI 29))
(clobber (reg:DI 26))]
"HAVE_AS_TLS"
[(set_attr "type" "multi")])
(define_insn_and_split "call_value_osf_tlsldm"
- [(set (match_operand 0 "" "")
- (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
+ [(set (match_operand 0)
+ (call (mem:DI (match_operand:DI 1 "symbolic_operand"))
(const_int 0)))
- (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
+ (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL)
(use (reg:DI 29))
(clobber (reg:DI 26))]
"HAVE_AS_TLS"
[(set_attr "type" "multi")])
(define_insn "*call_value_osf_1"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (reg:DI 29))
(clobber (reg:DI 26))]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
(set_attr "length" "12,*,16")])
(define_insn "*sibcall_value_osf_1_er"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
(set_attr "length" "*,8")])
(define_insn "*sibcall_value_osf_1"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
"! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
"@
; to generate relocs for VMS link to potentially optimize the call.
; Please do not molest.
(define_insn "*call_value_vms_1"
- [(set (match_operand 0 "" "")
+ [(set (match_operand 0)
(call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
- (match_operand 2 "" "")))
+ (match_operand 2)))
(use (match_operand:DI 3 "nonmemory_operand" "r,n"))
(use (reg:DI 25))
(use (reg:DI 26))
projects / thirdparty / gcc.git / commitdiff
