(define_insn_reservation "generic_branch" 1
(and (eq_attr "tune" "generic")
- (eq_attr "type" "branch,jump,call"))
+ (eq_attr "type" "branch,jump,call,jalr"))
"alu")
(define_insn_reservation "generic_imul" 10
/* True if attributes on current function have been checked. */
bool attributes_checked_p;
+ /* True if RA must be saved because of a far jump. */
+ bool far_jump_used;
+
/* The current frame information, calculated by riscv_compute_frame_info. */
struct riscv_frame_info frame;
any outermost HIGH.
'R' Print the low-part relocation associated with OP.
'C' Print the integer branch condition for comparison OP.
+ 'N' Print the inverse of the integer branch condition for comparison OP.
'A' Print the atomic operation suffix for memory model OP.
'I' Print the LR suffix for memory model OP.
'J' Print the SC suffix for memory model OP.
fputs (GET_RTX_NAME (code), file);
break;
+ case 'N':
+ /* The RTL names match the instruction names. */
+ fputs (GET_RTX_NAME (reverse_condition (code)), file);
+ break;
+
case 'A': {
const enum memmodel model = memmodel_base (INTVAL (op));
if (riscv_memmodel_needs_amo_acquire (model)
return set;
}
+/* Returns true if the current function might contain a far jump. */
+
+static bool
+riscv_far_jump_used_p ()
+{
+ size_t func_size = 0;
+
+ if (cfun->machine->far_jump_used)
+ return true;
+
+ /* We can't change far_jump_used during or after reload, as there is
+ no chance to change stack frame layout. So we must rely on the
+ conservative heuristic below having done the right thing. */
+ if (reload_in_progress || reload_completed)
+ return false;
+
+ /* Estimate the function length. */
+ for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
+ func_size += get_attr_length (insn);
+
+ /* Conservatively determine whether some jump might exceed 1 MiB
+ displacement. */
+ if (func_size * 2 >= 0x100000)
+ cfun->machine->far_jump_used = true;
+
+ return cfun->machine->far_jump_used;
+}
+
+/* Return true, if the current function must save the incoming return
+ address. */
+
+static bool
+riscv_save_return_addr_reg_p (void)
+{
+ /* The $ra register is call-clobbered: if this is not a leaf function,
+ save it. */
+ if (!crtl->is_leaf)
+ return true;
+
+ /* We need to save the incoming return address if __builtin_eh_return
+ is being used to set a different return address. */
+ if (crtl->calls_eh_return)
+ return true;
+
+ /* Far jumps/branches use $ra as a temporary to set up the target jump
+ location (clobbering the incoming return address). */
+ if (riscv_far_jump_used_p ())
+ return true;
+
+ /* Need not to use ra for leaf when frame pointer is turned off by
+ option whatever the omit-leaf-frame's value. */
+ if (frame_pointer_needed && crtl->is_leaf
+ && !TARGET_OMIT_LEAF_FRAME_POINTER)
+ return true;
+
+ return false;
+}
+
/* Return true if the current function must save register REGNO. */
static bool
if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
return true;
- /* Need not to use ra for leaf when frame pointer is turned off by option
- whatever the omit-leaf-frame's value. */
- bool keep_leaf_ra = frame_pointer_needed && crtl->is_leaf
- && !TARGET_OMIT_LEAF_FRAME_POINTER;
- if (regno == RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_leaf_ra))
+ if (regno == RETURN_ADDR_REGNUM && riscv_save_return_addr_reg_p ())
return true;
/* If this is an interrupt handler, then must save extra registers. */
#define FIXED_REGISTERS \
{ /* General registers. */ \
- 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
/* Floating-point registers. */ \
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
#define CALL_USED_REGISTERS \
{ /* General registers. */ \
- 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
/* Floating-point registers. */ \
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \
;; Classification of each insn.
;; branch conditional branch
-;; jump unconditional jump
+;; jump unconditional direct jump
+;; jalr unconditional indirect jump
+;; ret various returns, no arguments
;; call unconditional call
;; load load instruction(s)
;; fpload floating point load
;; vmov whole vector register move
;; vector unknown vector instruction
(define_attr "type"
- "unknown,branch,jump,call,load,fpload,store,fpstore,
+ "unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
;; Length of instruction in bytes.
(define_attr "length" ""
(cond [
+ ;; Branches further than +/- 1 MiB require three instructions.
;; Branches further than +/- 4 KiB require two instructions.
(eq_attr "type" "branch")
(if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 4088))
(le (minus (pc) (match_dup 0)) (const_int 4092)))
(const_int 4)
+ (if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 1048568))
+ (le (minus (pc) (match_dup 0)) (const_int 1048572)))
+ (const_int 8)
+ (const_int 12)))
+
+ ;; Jumps further than +/- 1 MiB require two instructions.
+ (eq_attr "type" "jump")
+ (if_then_else (and (le (minus (match_dup 0) (pc)) (const_int 1048568))
+ (le (minus (pc) (match_dup 0)) (const_int 1048572)))
+ (const_int 4)
(const_int 8))
;; Conservatively assume calls take two instructions (AUIPC + JALR).
(label_ref (match_operand 0 "" ""))
(pc)))]
""
- "b%C1\t%2,%z3,%0"
+{
+ if (get_attr_length (insn) == 12)
+ return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
+
+ return "b%C1\t%2,%z3,%l0";
+}
[(set_attr "type" "branch")
(set_attr "mode" "none")])
;; Unconditional branches.
(define_insn "jump"
- [(set (pc)
- (label_ref (match_operand 0 "" "")))]
+ [(set (pc) (label_ref (match_operand 0 "" "")))]
""
- "j\t%l0"
+{
+ /* Hopefully this does not happen often as this is going
+ to clobber $ra and muck up the return stack predictors. */
+ if (get_attr_length (insn) == 8)
+ return "call\t%l0";
+
+ return "j\t%l0";
+}
[(set_attr "type" "jump")
(set_attr "mode" "none")])
[(set (pc) (match_operand:P 0 "register_operand" "l"))]
""
"jr\t%0"
- [(set_attr "type" "jump")
+ [(set_attr "type" "jalr")
(set_attr "mode" "none")])
(define_expand "tablejump"
(use (label_ref (match_operand 1 "" "")))]
""
"jr\t%0"
- [(set_attr "type" "jump")
+ [(set_attr "type" "jalr")
(set_attr "mode" "none")])
;;
{
return riscv_output_return ();
}
- [(set_attr "type" "jump")
+ [(set_attr "type" "jalr")
(set_attr "mode" "none")])
;; Normal return.
(use (match_operand 0 "pmode_register_operand" ""))]
""
"jr\t%0"
- [(set_attr "type" "jump")
+ [(set_attr "type" "jalr")
(set_attr "mode" "none")])
;; This is used in compiling the unwind routines.
"epilogue_completed"
[(const_int 0)]
"riscv_expand_epilogue (EXCEPTION_RETURN); DONE;"
- [(set_attr "type" "jump")])
+ [(set_attr "type" "ret")])
;;
;; ....................
(const_int 0)]
""
""
- [(set_attr "type" "jump")])
+ [(set_attr "type" "ret")])
(define_insn "riscv_frcsr"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile [(const_int 0)] UNSPECV_MRET)]
""
"mret"
- [(set_attr "type" "jump")])
+ [(set_attr "type" "ret")])
(define_insn "riscv_sret"
[(return)
(unspec_volatile [(const_int 0)] UNSPECV_SRET)]
""
"sret"
- [(set_attr "type" "jump")])
+ [(set_attr "type" "ret")])
(define_insn "riscv_uret"
[(return)
(unspec_volatile [(const_int 0)] UNSPECV_URET)]
""
"uret"
- [(set_attr "type" "jump")])
+ [(set_attr "type" "ret")])
(define_insn "stack_tie<mode>"
[(set (mem:BLK (scratch))
(define_insn_reservation "sifive_7_jump" 1
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "jump,call"))
+ (eq_attr "type" "jump,call,jalr"))
"sifive_7_B")
(define_insn_reservation "sifive_7_mul" 3
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