drm/amd/display: Reset DSC memory status

[WHY]
When system exits idle state followed by enabling the display,
DSC memory may still be forced in a deep sleep or shutdown state.

Intermittent DSC corruption is seen when display is visible.

[HOW]
When DSC is enabled, reset dsc memory to force and disable status.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Duncan Ma <duncan.ma@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
index d6b2334d5364f8362d1d9812728e62fbec714e4e..75128fd3430671939a0f2320bb5ee6b844ebeeef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
@@ -32,16 +32,6 @@
 
 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);
 
-/* Object I/F functions */
-static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
-static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
-static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
-               struct dsc_optc_config *dsc_optc_cfg);
-static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
-static void dsc2_disable(struct display_stream_compressor *dsc);
-static void dsc2_disconnect(struct display_stream_compressor *dsc);
-static void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
-
 static const struct dsc_funcs dcn20_dsc_funcs = {
        .dsc_get_enc_caps = dsc2_get_enc_caps,
        .dsc_read_state = dsc2_read_state,
@@ -156,7 +146,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
  * into a dcn_dsc_state struct.
  */
-static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
+void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s)
 {
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 
@@ -173,7 +163,7 @@ static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_ds
 }
 
 
-static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
+bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
 {
        struct dsc_optc_config dsc_optc_cfg;
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
@@ -196,7 +186,7 @@ void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_conf
        DC_LOG_DSC("\tcolor_depth %d", config->color_depth);
 }
 
-static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
                struct dsc_optc_config *dsc_optc_cfg)
 {
        bool is_config_ok;
@@ -233,7 +223,7 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc
 }
 
 
-static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
+void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
 {
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
        int dsc_clock_en;
@@ -258,7 +248,7 @@ static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe)
 }
 
 
-static void dsc2_disable(struct display_stream_compressor *dsc)
+void dsc2_disable(struct display_stream_compressor *dsc)
 {
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
        int dsc_clock_en;
@@ -277,14 +267,14 @@ static void dsc2_disable(struct display_stream_compressor *dsc)
                DSC_CLOCK_EN, 0);
 }
 
-static void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
+void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc)
 {
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 
        REG_WAIT(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_DOUBLE_BUFFER_REG_UPDATE_PENDING, 0, 2, 50000);
 }
 
-static void dsc2_disconnect(struct display_stream_compressor *dsc)
+void dsc2_disconnect(struct display_stream_compressor *dsc)
 {
        struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
index a136b26c914c4197980b583c9aef1bf6eda4eb7f..a23308a785bca31243e57bfa372306958864eced 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
@@ -597,5 +597,14 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
                const struct dsc_config *dsc_cfg,
                uint8_t *dsc_packed_pps);
 
+void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
+bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
+void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
+               struct dsc_optc_config *dsc_optc_cfg);
+void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe);
+void dsc2_disable(struct display_stream_compressor *dsc);
+void dsc2_disconnect(struct display_stream_compressor *dsc);
+void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc);
+
 #endif
 

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
index 71d2dff9986d5f1f0fdc84afae3d360d765fb6ac..6f4f5a3c48614882de1d698743a3ddb3851b2f1d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
@@ -27,6 +27,20 @@
 #include "dcn35_dsc.h"
 #include "reg_helper.h"
 
+static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
+
+static const struct dsc_funcs dcn35_dsc_funcs = {
+       .dsc_get_enc_caps = dsc2_get_enc_caps,
+       .dsc_read_state = dsc2_read_state,
+       .dsc_validate_stream = dsc2_validate_stream,
+       .dsc_set_config = dsc2_set_config,
+       .dsc_get_packed_pps = dsc2_get_packed_pps,
+       .dsc_enable = dsc35_enable,
+       .dsc_disable = dsc2_disable,
+       .dsc_disconnect = dsc2_disconnect,
+       .dsc_wait_disconnect_pending_clear = dsc2_wait_disconnect_pending_clear,
+};
+
 /* Macro definitios for REG_SET macros*/
 #define CTX \
        dsc20->base.ctx
@@ -49,9 +63,47 @@ void dsc35_construct(struct dcn20_dsc *dsc,
                const struct dcn35_dsc_shift *dsc_shift,
                const struct dcn35_dsc_mask *dsc_mask)
 {
-       dsc2_construct(dsc, ctx, inst, dsc_regs,
-               (const struct dcn20_dsc_shift *)(dsc_shift),
-               (const struct dcn20_dsc_mask *)(dsc_mask));
+       dsc->base.ctx = ctx;
+       dsc->base.inst = inst;
+       dsc->base.funcs = &dcn35_dsc_funcs;
+
+       dsc->dsc_regs = dsc_regs;
+       dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift);
+       dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask);
+
+       dsc->max_image_width = 5184;
+}
+
+static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe)
+{
+       struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
+       int dsc_clock_en;
+       int dsc_fw_config;
+       int enabled_opp_pipe;
+
+       DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe);
+
+       // TODO: After an idle exit, the HW default values for power control
+       // are changed intermittently due to unknown reasons. There are cases
+       // when dscc memory are still in shutdown state during enablement.
+       // Reset power control to hw default values.
+       REG_UPDATE_2(DSCC_MEM_POWER_CONTROL,
+               DSCC_MEM_PWR_FORCE, 0,
+               DSCC_MEM_PWR_DIS, 0);
+
+       REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en);
+       REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe);
+       if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) {
+               DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe);
+               ASSERT(0);
+       }
+
+       REG_UPDATE(DSC_TOP_CONTROL,
+               DSC_CLOCK_EN, 1);
+
+       REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG,
+               DSCRM_DSC_FORWARD_EN, 1,
+               DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe);
 }
 
 void dsc35_set_fgcg(struct dcn20_dsc *dsc20, bool enable)