ARM: 9409/1: mmu: Do not use magic number for TTBCR settings

The code in early_paging_init is directly masking off bits
8, 9, 10 and 11 to temporarily disable caching of the translation
tables. There is some exlanations in the comment, but use some
defines instead of magic numbers so ut becomes more evident
what is going on.

Change the type of the register to u32 since these are indeed
unsigned 32bit registers, and use a temporary variable instead
of baking too much into the inline assembly call to increase
readability.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index dfab3e982cbf65e34e9eab7c47241a5b684eb296..944fc99555285331b6a2d56c02539517a70190e8 100644 (file)
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -106,6 +106,11 @@
 
 /*
  * TTBCR register bits.
+ *
+ * The ORGN0 and IRGN0 bits enables different forms of caching when
+ * walking the translation table. Clearing these bits (which is claimed
+ * to be the reset default) means "normal memory, [outer|inner]
+ * non-cacheable"
  */
 #define TTBCR_EAE              (1 << 31)
 #define TTBCR_IMP              (1 << 30)

diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 3f774856ca6763e9f6e34e44a829ea6a1371d01c..f85c177cdf8d2c3f116a2d377ef8b0a981a69a2c 100644 (file)
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1638,7 +1638,7 @@ static void __init early_paging_init(const struct machine_desc *mdesc)
 {
        pgtables_remap *lpae_pgtables_remap;
        unsigned long pa_pgd;
-       unsigned int cr, ttbcr;
+       u32 cr, ttbcr, tmp;
        long long offset;
 
        if (!mdesc->pv_fixup)
@@ -1688,7 +1688,9 @@ static void __init early_paging_init(const struct machine_desc *mdesc)
        cr = get_cr();
        set_cr(cr & ~(CR_I | CR_C));
        ttbcr = cpu_get_ttbcr();
-       cpu_set_ttbcr(ttbcr & ~(3 << 8 | 3 << 10));
+       /* Disable all kind of caching of the translation table */
+       tmp = ttbcr & ~(TTBCR_ORGN0_MASK | TTBCR_IRGN0_MASK);
+       cpu_set_ttbcr(tmp);
        flush_cache_all();
 
        /*