RISC-V: Add test cases for avg_ceil vaadd implementation

Add asm and run testcase for avg_ceil vaadd implementation.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/avg.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/avg_data.h: Add test data for
	avg_ceil.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c: New test.
	* gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
index 746c635ae5776113a6d55b18bc048fe54a5340f2..4aeb637bba7e1d294c92d8ad4c349386deb12865 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h
@@ -20,4 +20,21 @@ test_##NAME##_##WT##_##NT##_0(NT * restrict a, NT * restrict b, \
 #define RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) \
   RUN_AVG_0(NT, WT, NAME, a, b, out, n)
 
+#define DEF_AVG_1(NT, WT, NAME)                                 \
+__attribute__((noinline))                                       \
+void                                                            \
+test_##NAME##_##WT##_##NT##_1(NT * restrict a, NT * restrict b, \
+                             NT * restrict out, int n)         \
+{                                                               \
+  for (int i = 0; i < n; i++) {                                 \
+    out[i] = (NT)(((WT)a[i] + (WT)b[i] + 1) >> 1);              \
+  }                                                             \
+}
+#define DEF_AVG_1_WRAP(NT, WT, NAME) DEF_AVG_1(NT, WT, NAME)
+
+#define RUN_AVG_1(NT, WT, NAME, a, b, out, n) \
+  test_##NAME##_##WT##_##NT##_1(a, b, out, n)
+#define RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) \
+  RUN_AVG_1(NT, WT, NAME, a, b, out, n)
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c
new file mode 100644 (file)
index 0000000..138124c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int16_t
+#define WT int32_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c
new file mode 100644 (file)
index 0000000..30438c9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int16_t
+#define WT int64_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c
new file mode 100644 (file)
index 0000000..2e9cfa5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int32_t
+#define WT int64_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c
new file mode 100644 (file)
index 0000000..2ebf294
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int8_t
+#define WT int16_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c
new file mode 100644 (file)
index 0000000..64fec91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int8_t
+#define WT int32_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c
new file mode 100644 (file)
index 0000000..a72642c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "avg.h"
+
+#define NT int8_t
+#define WT int64_t
+
+DEF_AVG_1(NT, WT, avg_ceil)
+
+/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
new file mode 100644 (file)
index 0000000..1fa080b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int32_t
+#define NT   int16_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
new file mode 100644 (file)
index 0000000..deec763
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int64_t
+#define NT   int16_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
new file mode 100644 (file)
index 0000000..fa72000
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int64_t
+#define NT   int32_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
new file mode 100644 (file)
index 0000000..6865cf2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int16_t
+#define NT   int8_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
new file mode 100644 (file)
index 0000000..78620f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int32_t
+#define NT   int8_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
new file mode 100644 (file)
index 0000000..b2c763c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 -O3" } */
+
+#include "avg.h"
+#include "avg_data.h"
+
+#define WT   int64_t
+#define NT   int8_t
+#define NAME avg_ceil
+
+DEF_AVG_1_WRAP(NT, WT, NAME)
+
+#define TEST_DATA                            TEST_AVG_DATA_WRAP(NT, NAME)
+#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n)
+
+#include "avg_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
index cbeed147a565bd8329e1f5d6e3e5da2019c50f61..12b464a3ce27296e063068de9d7715c1ac6f8d4a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h
@@ -182,4 +182,180 @@ int64_t TEST_AVG_DATA(int64_t, avg_floor)[][3][N] =
   },
 };
 
+int8_t TEST_AVG_DATA(int8_t, avg_ceil)[][3][N] =
+{
+  {
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       8,  8,  8,  8,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+      -2, -2, -2, -2,
+       1,  1,  1,  1,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    {
+       127,  127,  127,  127,
+       127,  127,  127,  127,
+      -128, -128, -128, -128,
+      -128, -128, -128, -128,
+    },
+    {
+       126,  126,  126,  126,
+        -2,   -2,   -2,   -2,
+       127,  127,  127,  127,
+      -127, -127, -127, -127,
+    },
+    {
+       127,  127,  127,  127,
+        63,   63,   63,   63,
+         0,    0,    0,    0,
+      -127, -127, -127, -127,
+    },
+  },
+};
+
+int16_t TEST_AVG_DATA(int16_t, avg_ceil)[][3][N] =
+{
+  {
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       8,  8,  8,  8,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+      -2, -2, -2, -2,
+       1,  1,  1,  1,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    {
+       32767,  32767,  32767,  32767,
+       32767,  32767,  32767,  32767,
+      -32768, -32768, -32768, -32768,
+      -32768, -32768, -32768, -32768,
+    },
+    {
+       32766,  32766,  32766,  32766,
+          -2,     -2,     -2,     -2,
+       32767,  32767,  32767,  32767,
+      -32767, -32767, -32767, -32767,
+    },
+    {
+       32767,  32767,  32767,  32767,
+       16383,  16383,  16383,  16383,
+           0,      0,      0,      0,
+      -32767, -32767, -32767, -32767,
+    },
+  },
+};
+
+int32_t TEST_AVG_DATA(int32_t, avg_ceil)[][3][N] =
+{
+  {
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       8,  8,  8,  8,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+      -2, -2, -2, -2,
+       1,  1,  1,  1,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+    },
+    {
+       2147483646,  2147483646,  2147483646,  2147483646,
+               -2,          -2,          -2,          -2,
+       2147483647,  2147483647,  2147483647,  2147483647,
+      -2147483647, -2147483647, -2147483647, -2147483647,
+    },
+    {
+       2147483647,  2147483647,  2147483647,  2147483647,
+       1073741823,  1073741823,  1073741823,  1073741823,
+                0,           0,           0,           0,
+      -2147483647, -2147483647, -2147483647, -2147483647,
+    },
+  },
+};
+
+int64_t TEST_AVG_DATA(int64_t, avg_ceil)[][3][N] =
+{
+  {
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       8,  8,  8,  8,
+    },
+    {
+       0,  0,  0,  0,
+       0,  0,  0,  0,
+      -2, -2, -2, -2,
+       1,  1,  1,  1,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+       5,  5,  5,  5,
+    },
+  },
+  {
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+      -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull,
+    },
+    {
+       9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,  9223372036854775806ull,
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+                        -2ull,                   -2ull,                   -2ull,                   -2ull,
+      -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull,
+    },
+    {
+       9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,  9223372036854775807ull,
+       4611686018427387903ull,  4611686018427387903ull,  4611686018427387903ull,  4611686018427387903ull,
+                         0ull,                    0ull,                    0ull,                    0ull,
+      -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull,
+    },
+  },
+};
+
 #endif