ARM: dts: imx6ul/imx6ull: add boot phase properties

dtschema/schemas/bootph.yaml describe various node usage during
boot phases with DT.

All SoCs require buses (aips and spba), clock, iomuxc and SOC access
during boot process.

Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
index 6eb80f867f501c2b36c5daf096ca39f175b55fe1..24541fdf49ceb7a45160d43c563d32899ed60250 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
@@ -115,6 +115,7 @@
                #clock-cells = <0>;
                clock-frequency = <24000000>;
                clock-output-names = "osc";
+               bootph-pre-ram;
        };
 
        ipp_di0: clock-di0 {
@@ -143,6 +144,7 @@
                compatible = "simple-bus";
                interrupt-parent = <&gpc>;
                ranges;
+               bootph-pre-ram;
 
                ocram: sram@900000 {
                        compatible = "mmio-sram";
@@ -202,6 +204,7 @@
                        #size-cells = <1>;
                        reg = <0x02000000 0x100000>;
                        ranges;
+                       bootph-pre-ram;
 
                        spba-bus@2000000 {
                                compatible = "fsl,spba-bus", "simple-bus";
@@ -209,6 +212,7 @@
                                #size-cells = <1>;
                                reg = <0x02000000 0x40000>;
                                ranges;
+                               bootph-pre-ram;
 
                                ecspi1: spi@2008000 {
                                        #address-cells = <1>;
@@ -580,6 +584,7 @@
                                #clock-cells = <1>;
                                clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
                                clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
+                               bootph-pre-ram;
                        };
 
                        anatop: anatop@20c8000 {
@@ -745,6 +750,7 @@
                        iomuxc: pinctrl@20e0000 {
                                compatible = "fsl,imx6ul-iomuxc";
                                reg = <0x020e0000 0x4000>;
+                               bootph-pre-ram;
                        };
 
                        gpr: iomuxc-gpr@20e4000 {
@@ -826,6 +832,7 @@
                        #size-cells = <1>;
                        reg = <0x02100000 0x100000>;
                        ranges;
+                       bootph-pre-ram;
 
                        crypto: crypto@2140000 {
                                compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";

diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
index db0c339022accd8cd3fde95bce2dce3b13faee10..ba0ea10c7b74f3b346e417bf397e7149dbb65c9e 100644 (file)
--- a/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6ull.dtsi
@@ -57,6 +57,7 @@
                        #size-cells = <1>;
                        reg = <0x02200000 0x100000>;
                        ranges;
+                       bootph-pre-ram;
 
                        dcp: crypto@2280000 {
                                compatible = "fsl,imx6ull-dcp", "fsl,imx28-dcp";