net: stmmac: stm32: use PHY_INTF_SEL_x to select PHY interface

Convert dwmac-stm32 to use the PHY_INTF_SEL_x definitions.

For stm32mp1, the original definitions used constant 0 (GMII, 0 << 21),
BIT(21) (RGMII, 1 << 21) and BIT(23) (RMII, 4 << 21) to define these,
but from the values it can be clearly seen that these are the
PHY_INTF_SEL_x inputs to the dwmac.

For stm32mp2, the original definitions cover a bitfield 6:4 in the
SYSCFG Ethernet1 control register (according to documentation) and use
the PHY_INTF_SEL_x values.

Use the common dwmac definitions for the PHY interface selection field
by adding the bitfield mask, and using FIELD_PREP() for the bitfield
values.

This removes this incorrect use of BIT().

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vIjUK-0000000Dqtn-1AyK@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 6c179911ef3f1ce21c3e05e2934df096aa70d02c..1545772419d552a7cb28e7fb6b05b988da84d556 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -47,9 +47,13 @@
  *------------------------------------------
  */
 #define SYSCFG_PMCR_ETH_SEL_MII                BIT(20)
-#define SYSCFG_PMCR_ETH_SEL_RGMII      BIT(21)
-#define SYSCFG_PMCR_ETH_SEL_RMII       BIT(23)
-#define SYSCFG_PMCR_ETH_SEL_GMII       0
+#define SYSCFG_PMCR_PHY_INTF_SEL_MASK  GENMASK(23, 21)
+#define SYSCFG_PMCR_ETH_SEL_RGMII      \
+       FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, PHY_INTF_SEL_RGMII)
+#define SYSCFG_PMCR_ETH_SEL_RMII       \
+       FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, PHY_INTF_SEL_RMII)
+#define SYSCFG_PMCR_ETH_SEL_GMII       \
+       FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, PHY_INTF_SEL_GMII_MII)
 #define SYSCFG_MCU_ETH_SEL_MII         0
 #define SYSCFG_MCU_ETH_SEL_RMII                1
 
@@ -60,9 +64,13 @@
 #define SYSCFG_ETHCR_ETH_CLK_SEL       BIT(1)
 #define SYSCFG_ETHCR_ETH_REF_CLK_SEL   BIT(0)
 
-#define SYSCFG_ETHCR_ETH_SEL_MII       0
-#define SYSCFG_ETHCR_ETH_SEL_RGMII     BIT(4)
-#define SYSCFG_ETHCR_ETH_SEL_RMII      BIT(6)
+#define SYSCFG_ETHCR_ETH_SEL_MASK      GENMASK(6, 4)
+#define SYSCFG_ETHCR_ETH_SEL_MII       FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, \
+                                                  PHY_INTF_SEL_GMII_MII)
+#define SYSCFG_ETHCR_ETH_SEL_RGMII     FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, \
+                                                  PHY_INTF_SEL_RGMII)
+#define SYSCFG_ETHCR_ETH_SEL_RMII      FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, \
+                                                  PHY_INTF_SEL_RMII)
 
 /* STM32MPx register definitions
  *