5.4-stable patches

added patches:
	drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch

diff --git a/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch b/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch
new file mode 100644 (file)
index 0000000..2f44366
--- /dev/null
+++ b/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch
@@ -0,0 +1,46 @@
+From 7a6c6243b44a439bda4bf099032be35ebcf53406 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Wed, 3 Feb 2021 11:30:44 +0200
+Subject: drm/i915: Reject 446-480MHz HDMI clock on GLK
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 7a6c6243b44a439bda4bf099032be35ebcf53406 upstream.
+
+The BXT/GLK DPLL can't generate certain frequencies. We already
+reject the 233-240MHz range on both. But on GLK the DPLL max
+frequency was bumped from 300MHz to 594MHz, so now we get to
+also worry about the 446-480MHz range (double the original
+problem range). Reject any frequency within the higher
+problematic range as well.
+
+Cc: stable@vger.kernel.org
+Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3000
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20210203093044.30532-1-ville.syrjala@linux.intel.com
+Reviewed-by: Mika Kahola <mika.kahola@intel.com>
+(cherry picked from commit 41751b3e5c1ac656a86f8d45a8891115281b729e)
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/display/intel_hdmi.c |    6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
+@@ -2129,7 +2129,11 @@ hdmi_port_clock_valid(struct intel_hdmi
+       if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
+               return MODE_CLOCK_HIGH;
+ 
+-      /* BXT DPLL can't generate 223-240 MHz */
++      /* GLK DPLL can't generate 446-480 MHz */
++      if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
++              return MODE_CLOCK_RANGE;
++
++      /* BXT/GLK DPLL can't generate 223-240 MHz */
+       if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
+               return MODE_CLOCK_RANGE;
+ 

diff --git a/queue-5.4/series b/queue-5.4/series
index 237a4fcbc949fcf4deccea45734cef8efc3c3d7b..4672733967076699f1ef1d8ba8bdfcc1b4dba5ba 100644 (file)
--- a/queue-5.4/series
+++ b/queue-5.4/series
@@ -327,3 +327,4 @@ dm-era-fix-bitset-memory-leaks.patch
 dm-era-use-correct-value-size-in-equality-function-of-writeset-tree.patch
 dm-era-reinitialize-bitset-cache-before-digesting-a-new-writeset.patch
 dm-era-only-resize-metadata-in-preresume.patch
+drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch