drm: atmel-hlcdc: Define XLCDC specific registers

The register address of the XLCDC IP used in SAM9X7 SoC family
are different from the previous HLCDC. Defining those address
space with valid macros.

Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com>
[manikandan.m@microchip.com: Remove unused macro definitions]
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240424053351.589830-3-manikandan.m@microchip.com

diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
index d0ecf0f58cce2feefead4055f50efa354a91023e..c32e5c8809d7e2bfd2d37989a5a9e7db70e92b23 100644 (file)
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h
@@ -15,6 +15,7 @@
 
 #include <drm/drm_plane.h>
 
+/* LCD controller common registers */
 #define ATMEL_HLCDC_LAYER_CHER                 0x0
 #define ATMEL_HLCDC_LAYER_CHDR                 0x4
 #define ATMEL_HLCDC_LAYER_CHSR                 0x8
@@ -128,6 +129,47 @@
 
 #define ATMEL_HLCDC_MAX_LAYERS                 6
 
+/* XLCDC controller specific registers */
+#define ATMEL_XLCDC_LAYER_ENR                  0x10
+#define ATMEL_XLCDC_LAYER_EN                   BIT(0)
+
+#define ATMEL_XLCDC_LAYER_IER                  0x0
+#define ATMEL_XLCDC_LAYER_IDR                  0x4
+#define ATMEL_XLCDC_LAYER_ISR                  0xc
+#define ATMEL_XLCDC_LAYER_OVR_IRQ(p)           BIT(2 + (8 * (p)))
+
+#define ATMEL_XLCDC_LAYER_PLANE_ADDR(p)                (((p) * 0x4) + 0x18)
+
+#define ATMEL_XLCDC_LAYER_DMA_CFG              0
+
+#define ATMEL_XLCDC_LAYER_DMA                  BIT(0)
+#define ATMEL_XLCDC_LAYER_REP                  BIT(1)
+#define ATMEL_XLCDC_LAYER_DISCEN               BIT(4)
+
+#define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS    (4 << 6)
+#define ATMEL_XLCDC_LAYER_SFACTA_ONE           BIT(9)
+#define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS  (6 << 11)
+#define ATMEL_XLCDC_LAYER_DFACTA_ONE           BIT(14)
+
+#define ATMEL_XLCDC_LAYER_A0_SHIFT             16
+#define ATMEL_XLCDC_LAYER_A0(x)                        \
+       ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT)
+
+#define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE          BIT(0)
+#define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE                BIT(1)
+#define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE          BIT(4)
+#define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE                BIT(5)
+
+#define ATMEL_XLCDC_LAYER_VXSYCFG_ONE          BIT(0)
+#define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE      BIT(4)
+#define ATMEL_XLCDC_LAYER_VXSCCFG_ONE          BIT(16)
+#define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE      BIT(20)
+
+#define ATMEL_XLCDC_LAYER_HXSYCFG_ONE          BIT(0)
+#define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE      BIT(4)
+#define ATMEL_XLCDC_LAYER_HXSCCFG_ONE          BIT(16)
+#define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE      BIT(20)
+
 /**
  * Atmel HLCDC Layer registers layout structure
  *

diff --git a/include/linux/mfd/atmel-hlcdc.h b/include/linux/mfd/atmel-hlcdc.h
index a186119a49b57c246a2c502347c27bf562434d1f..80d675a03b3953c3e964c59ffb8aca8c06b5685d 100644 (file)
--- a/include/linux/mfd/atmel-hlcdc.h
+++ b/include/linux/mfd/atmel-hlcdc.h
@@ -22,6 +22,8 @@
 #define ATMEL_HLCDC_DITHER             BIT(6)
 #define ATMEL_HLCDC_DISPDLY            BIT(7)
 #define ATMEL_HLCDC_MODE_MASK          GENMASK(9, 8)
+#define ATMEL_XLCDC_MODE_MASK          GENMASK(10, 8)
+#define ATMEL_XLCDC_DPI                        BIT(11)
 #define ATMEL_HLCDC_PP                 BIT(10)
 #define ATMEL_HLCDC_VSPSU              BIT(12)
 #define ATMEL_HLCDC_VSPHO              BIT(13)
@@ -34,6 +36,12 @@
 #define ATMEL_HLCDC_IDR                        0x30
 #define ATMEL_HLCDC_IMR                        0x34
 #define ATMEL_HLCDC_ISR                        0x38
+#define ATMEL_XLCDC_ATTRE              0x3c
+
+#define ATMEL_XLCDC_BASE_UPDATE                BIT(0)
+#define ATMEL_XLCDC_OVR1_UPDATE                BIT(1)
+#define ATMEL_XLCDC_OVR3_UPDATE                BIT(2)
+#define ATMEL_XLCDC_HEO_UPDATE         BIT(3)
 
 #define ATMEL_HLCDC_CLKPOL             BIT(0)
 #define ATMEL_HLCDC_CLKSEL             BIT(2)
@@ -48,6 +56,8 @@
 #define ATMEL_HLCDC_DISP               BIT(2)
 #define ATMEL_HLCDC_PWM                        BIT(3)
 #define ATMEL_HLCDC_SIP                        BIT(4)
+#define ATMEL_XLCDC_SD                 BIT(5)
+#define ATMEL_XLCDC_CM                 BIT(6)
 
 #define ATMEL_HLCDC_SOF                        BIT(0)
 #define ATMEL_HLCDC_SYNCDIS            BIT(1)