--- /dev/null
+From 255b329ca7f0e9b5fa6da3a68bb713684fe10305 Mon Sep 17 00:00:00 2001
+From: Ilia Mirkin <imirkin@alum.mit.edu>
+Date: Sat, 7 Jun 2014 15:39:45 -0400
+Subject: drm/gk208/gr: add missing registers to grctx init
+
+From: Ilia Mirkin <imirkin@alum.mit.edu>
+
+commit 255b329ca7f0e9b5fa6da3a68bb713684fe10305 upstream.
+
+This fixes hangs on GK208 which happen instantaneously on trying to use a
+geometry shader.
+
+Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
++++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c
+@@ -545,10 +545,12 @@ nv108_grctx_generate_mods(struct nvc0_gr
+ mmio_list(0x408010, 0x80000000, 0, 0);
+ mmio_list(0x419004, 0x00000000, 8, 1);
+ mmio_list(0x419008, 0x00000000, 0, 0);
++ mmio_list(0x4064cc, 0x80000000, 0, 0);
+ mmio_list(0x408004, 0x00000000, 8, 0);
+ mmio_list(0x408008, 0x80000030, 0, 0);
+ mmio_list(0x418808, 0x00000000, 8, 0);
+ mmio_list(0x41880c, 0x80000030, 0, 0);
++ mmio_list(0x4064c8, 0x00c20200, 0, 0);
+ mmio_list(0x418810, 0x80000000, 12, 2);
+ mmio_list(0x419848, 0x10000000, 12, 2);
+
--- /dev/null
+From 562d55d991b39ce376c492df2f7890fd6a541ffc Mon Sep 17 00:00:00 2001
+From: Ben Widawsky <benjamin.widawsky@intel.com>
+Date: Tue, 27 May 2014 16:53:08 -0700
+Subject: drm/i915/bdw: Only use 2g GGTT for 32b platforms
+
+From: Ben Widawsky <benjamin.widawsky@intel.com>
+
+commit 562d55d991b39ce376c492df2f7890fd6a541ffc upstream.
+
+Daniel requested in the bug that I use a 3GB fallback size. Since this
+is not in the spec as a valid size, I decided against it. We could
+potentially add a patch to bump it to 3GB on top of this one.
+
+This probably should be CC: stable - but I'll let the powers that be
+decide that one.
+
+Regression from a revert of the revert:
+commit 7907f45bf9f67a1c5e5d4ae05bab428d7c2f43b2
+Author: Ben Widawsky <benjamin.widawsky@intel.com>
+Date: Wed Feb 19 22:05:46 2014 -0800
+
+ Revert "drm/i915/bdw: Limit GTT to 2GB"
+
+v2: Change ifdef to 32b, instead of ifndef
+update comment
+
+v3. Update comment to not wrap (Daniel).
+Update commit message
+
+v4: s/CONFIG_32/CONFIG_X86_32 (Jani).
+
+v5: s/CONFIG_x86_32BIT/CONFIG_x86_32, as meant in v4
+s/32B/32b (chris)
+
+Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76619
+Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
+Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
+Tested-by: "Yang, Guang A" <guang.a.yang@intel.com>
+Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
++++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
+@@ -1811,6 +1811,13 @@ static inline unsigned int gen8_get_tota
+ bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
+ if (bdw_gmch_ctl)
+ bdw_gmch_ctl = 1 << bdw_gmch_ctl;
++
++#ifdef CONFIG_X86_32
++ /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
++ if (bdw_gmch_ctl > 4)
++ bdw_gmch_ctl = 4;
++#endif
++
+ return bdw_gmch_ctl << 20;
+ }
+
--- /dev/null
+From e291af3f2259e9e105dfd72416fd5796513791a4 Mon Sep 17 00:00:00 2001
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+Date: Wed, 28 May 2014 05:22:18 +0200
+Subject: drm/nouveau/disp/nv04-nv40: abort scanoutpos query on vga analog.
+
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+
+commit e291af3f2259e9e105dfd72416fd5796513791a4 upstream.
+
+nv04_disp_scanoutpos() must abort to trigger simple timestamping
+fallback if vtotal/htotal regs return zero. This happens if the
+output isn't a digital output, but a vga analog output, as the
+regs don't get initialized in that case.
+
+Fixes timestamping failure on nv-40 and earlier with vga output.
+
+Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/core/engine/disp/nv04.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
++++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
+@@ -51,6 +51,14 @@ nv04_disp_scanoutpos(struct nouveau_obje
+ args->htotal = nv_rd32(priv, 0x680824 + (head * 0x2000)) & 0xffff;
+ args->hblanke = args->htotal - 1;
+
++ /*
++ * If output is vga instead of digital then vtotal/htotal is invalid
++ * so we have to give up and trigger the timestamping fallback in the
++ * drm core.
++ */
++ if (!args->vtotal || !args->htotal)
++ return -ENOTSUPP;
++
+ args->time[0] = ktime_to_ns(ktime_get());
+ line = nv_rd32(priv, 0x600868 + (head * 0x2000));
+ args->time[1] = ktime_to_ns(ktime_get());
--- /dev/null
+From af4870e406126b7ac0ae7c7ce5751f25ebe60f28 Mon Sep 17 00:00:00 2001
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+Date: Tue, 13 May 2014 00:42:08 +0200
+Subject: drm/nouveau/kms/nv04-nv40: fix pageflip events via special case.
+
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+
+commit af4870e406126b7ac0ae7c7ce5751f25ebe60f28 upstream.
+
+Cards with nv04 display engine can't reliably use vblank
+counts and timestamps computed via drm_handle_vblank(), as
+the function gets invoked after sending the pageflip events.
+
+Fix this by defaulting to the old crtcid = -1 fallback path
+on <= NV-50 cards, and only using the precise path on NV-50
+and later.
+
+Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_display.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/nouveau_display.c
++++ b/drivers/gpu/drm/nouveau/nouveau_display.c
+@@ -798,6 +798,7 @@ nouveau_finish_page_flip(struct nouveau_
+ struct drm_device *dev = drm->dev;
+ struct nouveau_page_flip_state *s;
+ unsigned long flags;
++ int crtcid = -1;
+
+ spin_lock_irqsave(&dev->event_lock, flags);
+
+@@ -808,8 +809,13 @@ nouveau_finish_page_flip(struct nouveau_
+ }
+
+ s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
+- if (s->event)
+- drm_send_vblank_event(dev, s->crtc, s->event);
++ if (s->event) {
++ /* Vblank timestamps/counts are only correct on >= NV-50 */
++ if (nv_device(drm->device)->card_type >= NV_50)
++ crtcid = s->crtc;
++
++ drm_send_vblank_event(dev, crtcid, s->event);
++ }
+
+ list_del(&s->head);
+ if (ps)
--- /dev/null
+From ba124a41058b300a5464206d2d33803cc3dc82ec Mon Sep 17 00:00:00 2001
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+Date: Wed, 11 Jun 2014 09:51:23 +0200
+Subject: drm/nouveau/kms: reference vblank for crtc during pageflip.
+
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+
+commit ba124a41058b300a5464206d2d33803cc3dc82ec upstream.
+
+Need to drm_vblank_get/put() the crtc involved in a
+pending pageflip, or we might not get vblank irqs and
+updates of vblank counts and timestamps for pageflip
+events and flip completion.
+
+Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/nouveau_display.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/nouveau/nouveau_display.c
++++ b/drivers/gpu/drm/nouveau/nouveau_display.c
+@@ -736,6 +736,9 @@ nouveau_crtc_page_flip(struct drm_crtc *
+ fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y,
+ new_bo->bo.offset };
+
++ /* Keep vblanks on during flip, for the target crtc of this flip */
++ drm_vblank_get(dev, nouveau_crtc(crtc)->index);
++
+ /* Emit a page flip */
+ if (nv_device(drm->device)->card_type >= NV_50) {
+ ret = nv50_display_flip_next(crtc, fb, chan, swap_interval);
+@@ -779,6 +782,7 @@ nouveau_crtc_page_flip(struct drm_crtc *
+ return 0;
+
+ fail_unreserve:
++ drm_vblank_put(dev, nouveau_crtc(crtc)->index);
+ ttm_bo_unreserve(&old_bo->bo);
+ fail_unpin:
+ mutex_unlock(&chan->cli->mutex);
+@@ -817,6 +821,9 @@ nouveau_finish_page_flip(struct nouveau_
+ drm_send_vblank_event(dev, crtcid, s->event);
+ }
+
++ /* Give up ownership of vblank for page-flipped crtc */
++ drm_vblank_put(dev, s->crtc);
++
+ list_del(&s->head);
+ if (ps)
+ *ps = *s;
--- /dev/null
+From dcfb1009df3b4ad8d2e0779dd45b438629d6858a Mon Sep 17 00:00:00 2001
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+Date: Wed, 19 Mar 2014 08:12:51 +0100
+Subject: drm/nv50-/mc: fix kms pageflip events by reordering irq handling order.
+
+From: Mario Kleiner <mario.kleiner.de@gmail.com>
+
+commit dcfb1009df3b4ad8d2e0779dd45b438629d6858a upstream.
+
+Whenever a single nouveau_mc_intr() main gpu irq-handler invocation was
+responsible for calling both, the vblank-irq handler (display engine irq)
+and kms-pageflip completion handler (from fifo irq), the order of
+invocation was wrong. nouveau_finish_flip() was called before
+drm_handle_vblank() for the vblank of pageflip completion, so the
+emitted pageflip event contained stale vblank count and timestamp
+from previous vblank. This caused failure in userspace to timestamp
+properly.
+
+Reorder order of invocation of engine irq handlers: Put
+NVDEV_ENGINE_DISP always on top, and thereby before NVDEV_ENGINE_FIFO,
+so that drm_handle_vblank() gets called to update vblank timestamps
+and count before potential pageflip events make use of that
+information.
+
+This works on nv-50 and later, where kms-pageflip completion triggers
+an irq either after a separate vblank irq, or both pageflip and vblank
+trigger one common irq invocation, but never before vblank irqs.
+
+v2 (Ben):
+- removed mods for nv04-nv40, it doesn't help there anyway
+- this is considered a hack, and a better solution should be found
+
+Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c | 2 +-
+ drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c | 2 +-
+ drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
++++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c
+@@ -26,6 +26,7 @@
+
+ const struct nouveau_mc_intr
+ nv50_mc_intr[] = {
++ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */
+ { 0x00000001, NVDEV_ENGINE_MPEG },
+ { 0x00000100, NVDEV_ENGINE_FIFO },
+ { 0x00001000, NVDEV_ENGINE_GR },
+@@ -34,7 +35,6 @@ nv50_mc_intr[] = {
+ { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */
+ { 0x00100000, NVDEV_SUBDEV_TIMER },
+ { 0x00200000, NVDEV_SUBDEV_GPIO },
+- { 0x04000000, NVDEV_ENGINE_DISP },
+ { 0x10000000, NVDEV_SUBDEV_BUS },
+ { 0x80000000, NVDEV_ENGINE_SW },
+ { 0x0002d101, NVDEV_SUBDEV_FB },
+--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
++++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c
+@@ -26,6 +26,7 @@
+
+ static const struct nouveau_mc_intr
+ nv98_mc_intr[] = {
++ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */
+ { 0x00000001, NVDEV_ENGINE_PPP },
+ { 0x00000100, NVDEV_ENGINE_FIFO },
+ { 0x00001000, NVDEV_ENGINE_GR },
+@@ -37,7 +38,6 @@ nv98_mc_intr[] = {
+ { 0x00100000, NVDEV_SUBDEV_TIMER },
+ { 0x00200000, NVDEV_SUBDEV_GPIO },
+ { 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */
+- { 0x04000000, NVDEV_ENGINE_DISP },
+ { 0x10000000, NVDEV_SUBDEV_BUS },
+ { 0x80000000, NVDEV_ENGINE_SW },
+ { 0x0042d101, NVDEV_SUBDEV_FB },
+--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
++++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
+@@ -26,6 +26,7 @@
+
+ const struct nouveau_mc_intr
+ nvc0_mc_intr[] = {
++ { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */
+ { 0x00000001, NVDEV_ENGINE_PPP },
+ { 0x00000020, NVDEV_ENGINE_COPY0 },
+ { 0x00000040, NVDEV_ENGINE_COPY1 },
+@@ -40,7 +41,6 @@ nvc0_mc_intr[] = {
+ { 0x00200000, NVDEV_SUBDEV_GPIO },
+ { 0x01000000, NVDEV_SUBDEV_PWR },
+ { 0x02000000, NVDEV_SUBDEV_LTCG },
+- { 0x04000000, NVDEV_ENGINE_DISP },
+ { 0x08000000, NVDEV_SUBDEV_FB },
+ { 0x10000000, NVDEV_SUBDEV_BUS },
+ { 0x40000000, NVDEV_SUBDEV_IBUS },
--- /dev/null
+From d71c48f69cc03912578472bced4cc43069fe07e1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 5 Jun 2014 23:01:03 -0400
+Subject: drm/radeon: add missing vce init case for hawaii
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit d71c48f69cc03912578472bced4cc43069fe07e1 upstream.
+
+Hawaii has the same version of VCE as other CIK parts.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_vce.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_vce.c
++++ b/drivers/gpu/drm/radeon/radeon_vce.c
+@@ -66,6 +66,7 @@ int radeon_vce_init(struct radeon_device
+ case CHIP_BONAIRE:
+ case CHIP_KAVERI:
+ case CHIP_KABINI:
++ case CHIP_HAWAII:
+ case CHIP_MULLINS:
+ fw_name = FIRMWARE_BONAIRE;
+ break;
--- /dev/null
+From 642528355c694f5ed68f6bff9ff520326a249f99 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 27 May 2014 16:40:51 -0400
+Subject: drm/radeon/atom: fix dithering on certain panels
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 642528355c694f5ed68f6bff9ff520326a249f99 upstream.
+
+We need to specify the encoder mode as LVDS for eDP
+when using the Crtc_Source atom table in order to properly
+set up the FMT hardware.
+
+bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=73911
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_encoders.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_encoders.c
++++ b/drivers/gpu/drm/radeon/atombios_encoders.c
+@@ -1884,8 +1884,11 @@ atombios_set_encoder_crtc_source(struct
+ args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
+ else
+ args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
+- } else
++ } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
++ args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
++ } else {
+ args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
++ }
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
--- /dev/null
+From b397207b7475afa9df2f94541f978100ff1ea47e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Wed, 2 Jul 2014 14:10:19 -0400
+Subject: drm/radeon/cik: fix typo in EOP packet
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit b397207b7475afa9df2f94541f978100ff1ea47e upstream.
+
+Volatile bit was in the wrong location. This bit is
+not used at the moment.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cikd.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/cikd.h
++++ b/drivers/gpu/drm/radeon/cikd.h
+@@ -1751,12 +1751,12 @@
+ #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
+ #define EOP_TCL1_ACTION_EN (1 << 16)
+ #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
++#define EOP_TCL2_VOLATILE (1 << 24)
+ #define EOP_CACHE_POLICY(x) ((x) << 25)
+ /* 0 - LRU
+ * 1 - Stream
+ * 2 - Bypass
+ */
+-#define EOP_TCL2_VOLATILE (1 << 27)
+ #define DATA_SEL(x) ((x) << 29)
+ /* 0 - discard
+ * 1 - send low 32bit data
--- /dev/null
+From 3b6d9fd23e015b5397c438fd3cd74147d2c805b6 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 27 May 2014 13:48:05 -0400
+Subject: drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 3b6d9fd23e015b5397c438fd3cd74147d2c805b6 upstream.
+
+Only DCE5+ asics support DP 1.2.
+
+Noticed by ArtForz on IRC.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_dp.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_dp.c
++++ b/drivers/gpu/drm/radeon/atombios_dp.c
+@@ -281,6 +281,19 @@ static int dp_get_max_dp_pix_clock(int l
+
+ /***** radeon specific DP functions *****/
+
++static int radeon_dp_get_max_link_rate(struct drm_connector *connector,
++ u8 dpcd[DP_DPCD_SIZE])
++{
++ int max_link_rate;
++
++ if (radeon_connector_is_dp12_capable(connector))
++ max_link_rate = min(drm_dp_max_link_rate(dpcd), 540000);
++ else
++ max_link_rate = min(drm_dp_max_link_rate(dpcd), 270000);
++
++ return max_link_rate;
++}
++
+ /* First get the min lane# when low rate is used according to pixel clock
+ * (prefer low rate), second check max lane# supported by DP panel,
+ * if the max lane# < low rate lane# then use max lane# instead.
+@@ -290,7 +303,7 @@ static int radeon_dp_get_dp_lane_number(
+ int pix_clock)
+ {
+ int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector));
+- int max_link_rate = drm_dp_max_link_rate(dpcd);
++ int max_link_rate = radeon_dp_get_max_link_rate(connector, dpcd);
+ int max_lane_num = drm_dp_max_lane_count(dpcd);
+ int lane_num;
+ int max_dp_pix_clock;
+@@ -328,7 +341,7 @@ static int radeon_dp_get_dp_link_clock(s
+ return 540000;
+ }
+
+- return drm_dp_max_link_rate(dpcd);
++ return radeon_dp_get_max_link_rate(connector, dpcd);
+ }
+
+ static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
--- /dev/null
+From e07929810f0a19ddd756558290c7d72827cbfcd9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 1 Jul 2014 12:07:33 -0400
+Subject: drm/radeon/dpm: fix typo in vddci setup for eg/btc
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit e07929810f0a19ddd756558290c7d72827cbfcd9 upstream.
+
+We were using the vddc mask rather than the vddci mask.
+
+Bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=79071
+
+Possibly also fixes:
+https://bugzilla.kernel.org/show_bug.cgi?id=68571
+
+Noticed-by: Jonathan Howard <jonathan@unbiased.name>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/cypress_dpm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/cypress_dpm.c
++++ b/drivers/gpu/drm/radeon/cypress_dpm.c
+@@ -1551,7 +1551,7 @@ int cypress_populate_smc_voltage_tables(
+
+ table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
+ table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
+- cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
++ cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
+ }
+
+ return 0;
--- /dev/null
+From b0880e87c1fd038b84498944f52e52c3e86ebe59 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 1 Jul 2014 12:11:31 -0400
+Subject: drm/radeon/dpm: fix vddci setup typo on cayman
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit b0880e87c1fd038b84498944f52e52c3e86ebe59 upstream.
+
+We were using the vddc mask rather than the vddci mask.
+
+Bug:
+https://bugzilla.kernel.org/show_bug.cgi?id=79071
+
+May also fix:
+https://bugs.freedesktop.org/show_bug.cgi?id=69723
+
+Noticed by: Dieter Nützel <Dieter@nuetzel-hh.de>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni_dpm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/ni_dpm.c
++++ b/drivers/gpu/drm/radeon/ni_dpm.c
+@@ -1315,7 +1315,7 @@ static void ni_populate_smc_voltage_tabl
+
+ table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
+ table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
+- cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
++ cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
+ }
+ }
+
--- /dev/null
+From af5d36539dfe043f1cf0f8b7334d6bb12cd14e75 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 27 May 2014 13:11:36 -0400
+Subject: drm/radeon: fix typo in radeon_connector_is_dp12_capable()
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit af5d36539dfe043f1cf0f8b7334d6bb12cd14e75 upstream.
+
+We were checking the ext clock rather than the display clock.
+
+Noticed by ArtForz on IRC.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_connectors.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_connectors.c
++++ b/drivers/gpu/drm/radeon/radeon_connectors.c
+@@ -1387,7 +1387,7 @@ bool radeon_connector_is_dp12_capable(st
+ struct radeon_device *rdev = dev->dev_private;
+
+ if (ASIC_IS_DCE5(rdev) &&
+- (rdev->clock.dp_extclk >= 53900) &&
++ (rdev->clock.default_dispclk >= 53900) &&
+ radeon_connector_encoder_is_hbr2(connector)) {
+ return true;
+ }
--- /dev/null
+From 7d5ab3009a8ca777174f6f469277b3922d56fd4b Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 21 Apr 2014 21:45:09 -0400
+Subject: drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 7d5ab3009a8ca777174f6f469277b3922d56fd4b upstream.
+
+May fix display issues with non-HDMI displays.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 48 +++++++++++++++++----------------
+ 1 file changed, 26 insertions(+), 22 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -862,14 +862,16 @@ static void atombios_crtc_program_pll(st
+ args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
+ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
+- switch (bpc) {
+- case 8:
+- default:
+- args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
+- break;
+- case 10:
+- args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
+- break;
++ if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
++ switch (bpc) {
++ case 8:
++ default:
++ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
++ break;
++ case 10:
++ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
++ break;
++ }
+ }
+ args.v5.ucTransmitterID = encoder_id;
+ args.v5.ucEncoderMode = encoder_mode;
+@@ -884,20 +886,22 @@ static void atombios_crtc_program_pll(st
+ args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
+ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
+- switch (bpc) {
+- case 8:
+- default:
+- args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
+- break;
+- case 10:
+- args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
+- break;
+- case 12:
+- args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
+- break;
+- case 16:
+- args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
+- break;
++ if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
++ switch (bpc) {
++ case 8:
++ default:
++ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
++ break;
++ case 10:
++ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
++ break;
++ case 12:
++ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
++ break;
++ case 16:
++ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
++ break;
++ }
+ }
+ args.v6.ucTransmitterID = encoder_id;
+ args.v6.ucEncoderMode = encoder_mode;
--- /dev/null
+From f034d87def51f026b735d1e2877e9387011b2ba3 Mon Sep 17 00:00:00 2001
+From: Pekon Gupta <pekon@ti.com>
+Date: Tue, 6 May 2014 09:41:32 +0530
+Subject: mtd: eLBC NAND: fix subpage write support
+
+From: Pekon Gupta <pekon@ti.com>
+
+commit f034d87def51f026b735d1e2877e9387011b2ba3 upstream.
+
+As subpage write is enabled by default for all drivers, nand_write_subpage_hwecc
+causes a crash if the driver did not register ecc->hwctl or ecc->calculate.
+This behavior was introduced in
+ commit 837a6ba4f3b6d23026674e6af6b6849a4634fff9
+ "mtd: nand: subpage write support for hardware based ECC schemes".
+
+This fixes a crash by emulating subpage write support by padding sub-page data
+with 0xff on either sides to make it full page compatible.
+
+Reported-by: Helmut Schaa <helmut.schaa@googlemail.com>
+Tested-by: Helmut Schaa <helmut.schaa@googlemail.com>
+Signed-off-by: Pekon Gupta <pekon@ti.com>
+Reviewed-by: Scott Wood <scottwood@freescale.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/nand/fsl_elbc_nand.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/mtd/nand/fsl_elbc_nand.c
++++ b/drivers/mtd/nand/fsl_elbc_nand.c
+@@ -723,6 +723,19 @@ static int fsl_elbc_write_page(struct mt
+ return 0;
+ }
+
++/* ECC will be calculated automatically, and errors will be detected in
++ * waitfunc.
++ */
++static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
++ uint32_t offset, uint32_t data_len,
++ const uint8_t *buf, int oob_required)
++{
++ fsl_elbc_write_buf(mtd, buf, mtd->writesize);
++ fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
++
++ return 0;
++}
++
+ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
+ {
+ struct fsl_lbc_ctrl *ctrl = priv->ctrl;
+@@ -761,6 +774,7 @@ static int fsl_elbc_chip_init(struct fsl
+
+ chip->ecc.read_page = fsl_elbc_read_page;
+ chip->ecc.write_page = fsl_elbc_write_page;
++ chip->ecc.write_subpage = fsl_elbc_write_subpage;
+
+ /* If CS Base Register selects full hardware ECC then use it */
+ if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) ==
--- /dev/null
+From f306e8c3b667632952f1a4a74ffb910bbc06255f Mon Sep 17 00:00:00 2001
+From: pekon gupta <pekon@ti.com>
+Date: Thu, 20 Mar 2014 18:49:58 +0530
+Subject: mtd: nand: omap: fix BCHx ecc.correct to return detected bit-flips in erased-page
+
+From: pekon gupta <pekon@ti.com>
+
+commit f306e8c3b667632952f1a4a74ffb910bbc06255f upstream.
+
+fixes: commit 62116e5171e00f85a8d53f76e45b84423c89ff34
+ mtd: nand: omap2: Support for hardware BCH error correction.
+
+In omap_elm_correct_data(), if bitflip_count in an erased-page is within the
+correctable limit (< ecc.strength), then it is not indicated back to the caller
+ecc->read_page().
+
+This mis-guides upper layers like MTD and UBIFS layer to assume erased-page as
+perfectly clean and use it for writing even if actual bitflip_count was
+dangerously high (bitflip_count > mtd->bitflip_threshold).
+
+This patch fixes this above issue, by returning 'stats' to caller
+ecc->read_page() under all scenarios.
+
+Reported-by: Brian Norris <computersforpeace@gmail.com>
+Signed-off-by: Pekon Gupta <pekon@ti.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/nand/omap2.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/omap2.c
++++ b/drivers/mtd/nand/omap2.c
+@@ -1382,7 +1382,7 @@ static int omap_elm_correct_data(struct
+
+ /* Check if any error reported */
+ if (!is_error_reported)
+- return 0;
++ return stat;
+
+ /* Decode BCH error using ELM module */
+ elm_decode_bch_error_page(info->elm_dev, ecc_vec, err_vec);
--- /dev/null
+From b7e460624f0f3c31150f3b09e75b0d009e22ba5f Mon Sep 17 00:00:00 2001
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Date: Thu, 22 May 2014 14:56:52 +0200
+Subject: mtd: pxa3xx_nand: make the driver work on big-endian systems
+
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+
+commit b7e460624f0f3c31150f3b09e75b0d009e22ba5f upstream.
+
+The pxa3xx_nand driver currently uses __raw_writel() and __raw_readl()
+to access I/O registers. However, those functions do not do any
+endianness swapping, which means that they won't work when the CPU
+runs in big-endian but the I/O registers are little endian, which is
+the common situation for ARM systems running big endian.
+
+Since __raw_writel() and __raw_readl() do not include any memory
+barriers and the pxa3xx_nand driver can only be compiled for ARM
+platforms, the closest I/o accessors functions that do endianess
+swapping are writel_relaxed() and readl_relaxed().
+
+This patch has been verified to work on Armada XP GP: without the
+patch, the NAND is not detected when the kernel runs big endian while
+it is properly detected when the kernel runs little endian. With the
+patch applied, the NAND is properly detected in both situations
+(little and big endian).
+
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+Signed-off-by: Brian Norris <computersforpeace@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/mtd/nand/pxa3xx_nand.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/nand/pxa3xx_nand.c
++++ b/drivers/mtd/nand/pxa3xx_nand.c
+@@ -127,10 +127,10 @@
+
+ /* macros for registers read/write */
+ #define nand_writel(info, off, val) \
+- __raw_writel((val), (info)->mmio_base + (off))
++ writel_relaxed((val), (info)->mmio_base + (off))
+
+ #define nand_readl(info, off) \
+- __raw_readl((info)->mmio_base + (off))
++ readl_relaxed((info)->mmio_base + (off))
+
+ /* error code and state */
+ enum {
usb-gadget-f_fs-fix-null-pointer-dereference-when-there-are-no-strings.patch
rt2x00-disable-tkip-on-usb.patch
rt2x00-fix-rfkill-regression-on-rt2500pci.patch
+mtd-elbc-nand-fix-subpage-write-support.patch
+mtd-nand-omap-fix-bchx-ecc.correct-to-return-detected-bit-flips-in-erased-page.patch
+mtd-pxa3xx_nand-make-the-driver-work-on-big-endian-systems.patch
+vgaswitcheroo-switch-the-mux-to-the-igp-on-power-down-when.patch
+drm-nouveau-kms-nv04-nv40-fix-pageflip-events-via-special-case.patch
+drm-nouveau-disp-nv04-nv40-abort-scanoutpos-query-on-vga-analog.patch
+drm-nouveau-kms-reference-vblank-for-crtc-during-pageflip.patch
+drm-radeon-only-apply-hdmi-bpc-pll-flags-when-encoder-mode-is-hdmi.patch
+drm-radeon-fix-typo-in-radeon_connector_is_dp12_capable.patch
+drm-radeon-dp-fix-lane-clock-setup-for-dp-1.2-capable-devices.patch
+drm-radeon-atom-fix-dithering-on-certain-panels.patch
+drm-radeon-add-missing-vce-init-case-for-hawaii.patch
+drm-radeon-dpm-fix-typo-in-vddci-setup-for-eg-btc.patch
+drm-radeon-dpm-fix-vddci-setup-typo-on-cayman.patch
+drm-radeon-cik-fix-typo-in-eop-packet.patch
+drm-nv50-mc-fix-kms-pageflip-events-by-reordering-irq-handling-order.patch
+drm-gk208-gr-add-missing-registers-to-grctx-init.patch
+drm-i915-bdw-only-use-2g-ggtt-for-32b-platforms.patch
--- /dev/null
+From f2bc561610962693be61425cf913778586d8f9c1 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 19 May 2014 14:04:43 -0400
+Subject: vgaswitcheroo: switch the mux to the igp on power down when
+ runpm is enabled
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit f2bc561610962693be61425cf913778586d8f9c1 upstream.
+
+Avoids blank screens on muxed systems when runpm is active.
+
+bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=75917
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/vga/vga_switcheroo.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/vga/vga_switcheroo.c
++++ b/drivers/gpu/vga/vga_switcheroo.c
+@@ -623,7 +623,8 @@ static int vga_switcheroo_runtime_suspen
+ ret = dev->bus->pm->runtime_suspend(dev);
+ if (ret)
+ return ret;
+-
++ if (vgasr_priv.handler->switchto)
++ vgasr_priv.handler->switchto(VGA_SWITCHEROO_IGD);
+ vga_switcheroo_power_switch(pdev, VGA_SWITCHEROO_OFF);
+ return 0;
+ }
projects / thirdparty / kernel / stable-queue.git / commitdiff
