if (which_alternative == 4 || which_alternative == 7)
{
- rtx ops[2];
- int regno = (which_alternative == 7)
- ? REGNO (operands[1]) : REGNO (operands[0]);
-
- ops[0] = operands[0];
- ops[1] = operands[1];
- if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode)
- {
- if (which_alternative == 7)
- {
- ops[1] = gen_rtx_REG (DImode, regno);
- output_asm_insn ("vstr.64\t%P1, %E0",ops);
- }
- else
- {
- ops[0] = gen_rtx_REG (DImode, regno);
- output_asm_insn ("vldr.64\t%P0, %E1",ops);
- }
- }
- else if (<MODE>mode == TImode)
+ if (<MODE>mode == V2DFmode || <MODE>mode == V2DImode || <MODE>mode == TImode)
{
if (which_alternative == 7)
- output_asm_insn ("vstr.64\t%q1, %E0",ops);
+ output_asm_insn ("vstrw.32\t%q1, %E0", operands);
else
- output_asm_insn ("vldr.64\t%q0, %E1",ops);
+ output_asm_insn ("vldrw.u32\t%q0, %E1",operands);
}
else
{
if (which_alternative == 7)
- {
- ops[1] = gen_rtx_REG (TImode, regno);
- output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0",ops);
- }
+ output_asm_insn ("vstr<V_sz_elem1>.<V_sz_elem>\t%q1, %E0", operands);
else
- {
- ops[0] = gen_rtx_REG (TImode, regno);
- output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1",ops);
- }
+ output_asm_insn ("vldr<V_sz_elem1>.<V_sz_elem>\t%q0, %E1", operands);
}
return "";
}
}
/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldr.64" 1 } } */
-/* { dg-final { scan-assembler-times "vstr.64" 1 } } */
+/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
+/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
}
/* { dg-final { scan-assembler "vldrd.64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldr.64" 1 } } */
-/* { dg-final { scan-assembler-times "vstr.64" 1 } } */
+/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
+/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldr.64" 1 } } */
-/* { dg-final { scan-assembler-times "vstr.64" 1 } } */
+/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
+/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */
/* { dg-final { scan-assembler "vpst" } } */
/* { dg-final { scan-assembler "vldrdt.u64\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */
-/* { dg-final { scan-assembler-times "vldr.64" 1 } } */
-/* { dg-final { scan-assembler-times "vstr.64" 1 } } */
+/* { dg-final { scan-assembler-times "vldrw.u32" 1 } } */
+/* { dg-final { scan-assembler-times "vstrw.32" 1 } } */
/* { dg-final { scan-assembler-not "__ARM_undef" } } */