drm/i915/xe3lpd: Add check to see if edp over type c is allowed

Read PICA register to see if edp over type C is possible and then
add the appropriate tables for it.

--v2
-remove bool from intel_encoder have it in runtime_info [Jani]
-initialize the bool in runtime_info init [Jani]
-dont abbreviate the bool [Jani]

--v3
-Remove useless display version check [Jani]
-change the warn on condition [Jani]
-no need for a different function for edp type c check [Jani]
-dont add register in i915_reg [Jani]

Bspec: 68846
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241028193015.3241858-3-clinton.a.taylor@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index def08a8d4c6bb951ad40e76a3ae26ecabbf4990e..740b18bfc22f6ce07e6f0e110090a1d4a32a1023 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2265,9 +2265,12 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
                         struct intel_encoder *encoder)
 {
        struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+       struct intel_display *display = to_intel_display(crtc_state);
 
        if (intel_crtc_has_dp_encoder(crtc_state)) {
                if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+                       if (DISPLAY_RUNTIME_INFO(display)->edp_typec_support)
+                               return xe3lpd_c20_dp_edp_tables;
                        if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
                                return xe2hpd_c20_edp_tables;
                }

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index fdce4152a7c951d2880d4887fcbbeebfc26704c8..582d6277d20cebc6d4666231b53d2cd493597f43 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -365,4 +365,7 @@
 #define HDMI_DIV_MASK          REG_GENMASK16(2, 0)
 #define HDMI_DIV(val)          REG_FIELD_PREP16(HDMI_DIV_MASK, val)
 
+#define PICA_PHY_CONFIG_CONTROL                _MMIO(0x16FE68)
+#define   EDP_ON_TYPEC                 REG_BIT(31)
+
 #endif /* __INTEL_CX0_REG_DEFS_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 1a52b0911407c409ba5d7b8db7ec1255a782559d..9031b85bb0008aa83a6ef923e90fe43aa5fcbd6a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -9,6 +9,7 @@
 
 #include "i915_drv.h"
 #include "i915_reg.h"
+#include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
 #include "intel_display_device.h"
@@ -1685,6 +1686,10 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9
                }
        }
 
+       if (DISPLAY_VER(i915) >= 30)
+               display_runtime->edp_typec_support =
+                       intel_de_read(display, PICA_PHY_CONFIG_CONTROL) & EDP_ON_TYPEC;
+
        display_runtime->rawclk_freq = intel_read_rawclk(display);
        drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq);
 

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 071a36b51f79f93a4dd04d8a94b58ef014d87fe8..410f8b33a8a1df51461135377ff261c9b808a585 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -232,6 +232,7 @@ struct intel_display_runtime_info {
        bool has_hdcp;
        bool has_dmc;
        bool has_dsc;
+       bool edp_typec_support;
 };
 
 struct intel_display_device_info {

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9dd4610c749a89f607adfc4d9f95bbf1264082e6..694491a4c408b8ab3a0cb7cca9bee51f91055f9c 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6444,10 +6444,11 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
        if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
                /*
-                * Currently we don't support eDP on TypeC ports, although in
-                * theory it could work on TypeC legacy ports.
+                * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
+                * although in theory it could work on TypeC legacy ports.
                 */
-               drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder));
+               drm_WARN_ON(dev, intel_encoder_is_tc(intel_encoder) &&
+                           DISPLAY_VER(dev_priv) < 30);
                type = DRM_MODE_CONNECTOR_eDP;
                intel_encoder->type = INTEL_OUTPUT_EDP;