clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers

All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index fde934151b57c4d630ba41fb32c9b8a580b0b3a5..53a58034bef45bc08d00f7302481714e99157434 100644 (file)
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -99,8 +99,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
        DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
        DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
        DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
-       DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
-               DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
        DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
        DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
        DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
@@ -108,21 +107,16 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
        DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
 
        /* Core output clk */
-       DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
-               CLK_DIVIDER_HIWORD_MASK),
-       DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
-               dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("I", R9A07G043_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
+       DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
        DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
        DEF_FIXED("TSU", R9A07G043_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
-       DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
-               DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
        DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
-       DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2,
-               DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+       DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
        DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
        DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
-       DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2,
-               sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
+       DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
        DEF_FIXED("SPI0", R9A07G043_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
        DEF_FIXED("SPI1", R9A07G043_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
        DEF_SD_MUX("SD0", R9A07G043_CLK_SD0, SEL_SDHI0, sel_shdi),

diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index ee442684453b16be80082ec96924f62699f8f70e..8255b39dc147c561288414b25cfc6c94e2a63138 100644 (file)
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -139,8 +139,7 @@ static const struct {
                DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
                DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),
                DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
-               DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,
-                       DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+               DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
 
                DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),
                DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
@@ -149,32 +148,26 @@ static const struct {
                DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
                DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),
                DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
-                       DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK),
+                       DIVDSILPCLK, dtable_16_128),
 
                /* Core output clk */
-               DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
-                       CLK_DIVIDER_HIWORD_MASK),
-               DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
-                       dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+               DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8),
+               DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A, dtable_1_32),
                DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2),
                DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV2_10, 1, 1),
-               DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4,
-                       DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+               DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, DIVPL3B, dtable_1_32),
                DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G044_CLK_P1, 1, 2),
-               DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2,
-                       DIVPL3A, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+               DEF_DIV("P2", R9A07G044_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
                DEF_FIXED("M0", R9A07G044_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
                DEF_FIXED("ZT", R9A07G044_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
-               DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2,
-                       sel_pll6_2, 0, CLK_MUX_HIWORD_MASK),
+               DEF_MUX("HP", R9A07G044_CLK_HP, SEL_PLL6_2, sel_pll6_2),
                DEF_FIXED("SPI0", R9A07G044_CLK_SPI0, CLK_DIV_PLL3_C, 1, 2),
                DEF_FIXED("SPI1", R9A07G044_CLK_SPI1, CLK_DIV_PLL3_C, 1, 4),
                DEF_SD_MUX("SD0", R9A07G044_CLK_SD0, SEL_SDHI0, sel_shdi),
                DEF_SD_MUX("SD1", R9A07G044_CLK_SD1, SEL_SDHI1, sel_shdi),
                DEF_FIXED("SD0_DIV4", CLK_SD0_DIV4, R9A07G044_CLK_SD0, 1, 4),
                DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
-               DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
-                       CLK_DIVIDER_HIWORD_MASK),
+               DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8),
                DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
                DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
                DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),

diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index a6004f0b415a478328e3321a7c513aa19c0ef2ed..59bbc8942e1db741d69e33d5b49a5d874fa30d3a 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -135,18 +135,19 @@ enum clk_types {
        DEF_TYPE(_name, _id, CLK_TYPE_IN)
 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \
        DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
-#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \
+#define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
        DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
-                .parent = _parent, .dtable = _dtable, .flag = _flag)
+                .parent = _parent, .dtable = _dtable, \
+                .flag = CLK_DIVIDER_HIWORD_MASK)
 #define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \
        DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \
                 .parent = _parent, .dtable = _dtable, \
                 .flag = CLK_DIVIDER_READ_ONLY)
-#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \
+#define DEF_MUX(_name, _id, _conf, _parent_names) \
        DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
                 .parent_names = _parent_names, \
                 .num_parents = ARRAY_SIZE(_parent_names), \
-                .flag = _flag, .mux_flags = _mux_flags)
+                .mux_flags = CLK_MUX_HIWORD_MASK)
 #define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
        DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
                 .parent_names = _parent_names, \