drm/amd/amdgpu: Enable MMHUB prefetch for ISP v4.1.0 and 4.1.1

Remove temporary WA to disable ISP prefetch as MMHUB SAW is initialized
to support ISP HW access GART memory using the TLSi path with prefetch
enabled.

Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
index 962da37fb1f7381e5613300746551da16211da13..aac107898baeccb2541b7b00ac5b588e5d949c10 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.c
@@ -104,18 +104,6 @@ static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp)
                goto failure;
        }
 
-       /*
-        * Temporary WA added to disable MMHUB TLSi until the GART initialization
-        * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
-        * using the TLSi path
-        */
-       WREG32(mmDAGB0_WRCLI5_V4_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB0_WRCLI9_V4_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB0_WRCLI10_V4_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB0_WRCLI14_V4_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB0_WRCLI19_V4_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB0_WRCLI20_V4_1 >> 2, 0xFE5FEAA8);
-
        return 0;
 
 failure:

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
index bd9e1f13c74812c628e75c190c81ea8e4952e06f..315f2822410c0e224c9f8dd2f3d744c570058fa7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_0.h
@@ -32,13 +32,6 @@
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
-#define mmDAGB0_WRCLI5_V4_1    0x6811C
-#define mmDAGB0_WRCLI9_V4_1    0x6812C
-#define mmDAGB0_WRCLI10_V4_1   0x68130
-#define mmDAGB0_WRCLI14_V4_1   0x68140
-#define mmDAGB0_WRCLI19_V4_1   0x68154
-#define mmDAGB0_WRCLI20_V4_1   0x68158
-
 #define MAX_ISP410_INT_SRC 8
 
 void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp);

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
index 67f95f05ecca2e447da8b33e20a5206b04c8c1d1..4e17fa03f7b5f23b5ae134ddd486a4a88eacd5fc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.c
@@ -104,18 +104,6 @@ static int isp_v4_1_1_hw_init(struct amdgpu_isp *isp)
                goto failure;
        }
 
-       /*
-        * Temporary WA added to disable MMHUB TLSi until the GART initialization
-        * is ready to support MMHUB TLSi and SAW for ISP HW to access GART memory
-        * using the TLSi path
-        */
-       WREG32(mmDAGB1_WRCLI5_V4_1_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB1_WRCLI9_V4_1_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB1_WRCLI10_V4_1_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB1_WRCLI14_V4_1_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB1_WRCLI19_V4_1_1 >> 2, 0xFE5FEAA8);
-       WREG32(mmDAGB1_WRCLI20_V4_1_1 >> 2, 0xFE5FEAA8);
-
        return 0;
 
 failure:

diff --git a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
index 6bfb1de191a028c8348997b05f42ae0b482fef95..dfb9522c9d6a2a2b1b08a3ec37c0772528aa7125 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/isp_v4_1_1.h
@@ -32,13 +32,6 @@
 
 #include "ivsrcid/isp/irqsrcs_isp_4_1.h"
 
-#define mmDAGB1_WRCLI5_V4_1_1   0x68420
-#define mmDAGB1_WRCLI9_V4_1_1   0x68430
-#define mmDAGB1_WRCLI10_V4_1_1  0x68434
-#define mmDAGB1_WRCLI14_V4_1_1  0x68444
-#define mmDAGB1_WRCLI19_V4_1_1  0x68458
-#define mmDAGB1_WRCLI20_V4_1_1  0x6845C
-
 #define MAX_ISP411_INT_SRC 8
 
 void isp_v4_1_1_set_isp_funcs(struct amdgpu_isp *isp);