* config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64

	restriction for ISA_MIPS32R2.
	(ISA_HAS_LXC1_SXC1): New macro.
	(ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
	(ISA_HAS_NMADD4_NMSUB4): Likewise.
	(ISA_HAS_FP_RECIP_RSQRT): Likewise.
	(ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.
	* config/mips/mips.md (*<ANYF:loadx>_<P:mode>): Use
	ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4.
	(*<ANYF:storex>_<P:mode>): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@205130 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c93f358ffa2664ec9cffddbcf387d4f6b4d8a9d1..485dc55ae1047406511863991adc70840b8915bc 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2013-11-20  Maciej W. Rozycki  <macro@codesourcery.com>
+
+       * config/mips/mips.h (ISA_HAS_FP4): Remove TARGET_FLOAT64
+       restriction for ISA_MIPS32R2.
+       (ISA_HAS_LXC1_SXC1): New macro.
+       (ISA_HAS_FP_MADD4_MSUB4): Remove ISA_MIPS32R2 special-casing.
+       (ISA_HAS_NMADD4_NMSUB4): Likewise.
+       (ISA_HAS_FP_RECIP_RSQRT): Likewise.
+       (ISA_HAS_PREFETCHX): Redefine in terms of ISA_HAS_FP4.
+       * config/mips/mips.md (*<ANYF:loadx>_<P:mode>): Use
+       ISA_HAS_LXC1_SXC1 rather than ISA_HAS_FP4.
+       (*<ANYF:storex>_<P:mode>): Likewise.
+
 2013-11-20  Maciej W. Rozycki  <macro@codesourcery.com>
 
        * config/mips/mips.h (ISA_HAS_FP_RECIP_RSQRT): New macro.

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 97df90030008991608380a65a655751d6b61716a..021419c0a6a1f44d0d43e8e8746e225ebb6fce6d 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -882,13 +882,18 @@ struct mips_cpu_info {
 
 /* This is a catch all for other mips4 instructions: indexed load, the
    FP madd and msub instructions, and the FP recip and recip sqrt
-   instructions.  */
+   instructions.  Note that this macro should only be used by other
+   ISA_HAS_* macros.  */
 #define ISA_HAS_FP4            ((ISA_MIPS4                             \
-                                 || (ISA_MIPS32R2 && TARGET_FLOAT64)   \
+                                 || ISA_MIPS32R2                       \
                                  || ISA_MIPS64                         \
                                  || ISA_MIPS64R2)                      \
                                 && !TARGET_MIPS16)
 
+/* ISA has floating-point indexed load and store instructions
+   (LWXC1, LDXC1, SWXC1 and SDXC1).  */
+#define ISA_HAS_LXC1_SXC1      ISA_HAS_FP4
+
 /* ISA has paired-single instructions.  */
 #define ISA_HAS_PAIRED_SINGLE  (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
 
@@ -906,16 +911,14 @@ struct mips_cpu_info {
 #define GENERATE_MADD_MSUB     (TARGET_IMADD && !TARGET_MIPS16)
 
 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'.  */
-#define ISA_HAS_FP_MADD4_MSUB4  (ISA_HAS_FP4                           \
-                                || (ISA_MIPS32R2 && !TARGET_MIPS16))
+#define ISA_HAS_FP_MADD4_MSUB4  ISA_HAS_FP4
 
 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'.  */
 #define ISA_HAS_FP_MADD3_MSUB3  TARGET_LOONGSON_2EF
 
 /* ISA has floating-point nmadd and nmsub instructions
    'd = -((a * b) [+-] c)'.  */
-#define ISA_HAS_NMADD4_NMSUB4  (ISA_HAS_FP4                            \
-                                || (ISA_MIPS32R2 && !TARGET_MIPS16))
+#define ISA_HAS_NMADD4_NMSUB4  ISA_HAS_FP4
 
 /* ISA has floating-point nmadd and nmsub instructions
    'c = -((a * b) [+-] c)'.  */
@@ -926,7 +929,7 @@ struct mips_cpu_info {
    doubles are stored in pairs of FPRs, so for safety's sake, we apply
    this restriction to the MIPS IV ISA too.  */
 #define ISA_HAS_FP_RECIP_RSQRT(MODE)                                   \
-                               ((((ISA_HAS_FP4 || ISA_MIPS32R2)        \
+                               (((ISA_HAS_FP4                          \
                                   && ((MODE) == SFmode                 \
                                       || ((TARGET_FLOAT64              \
                                            || ISA_MIPS32R2             \
@@ -1006,11 +1009,7 @@ struct mips_cpu_info {
    'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
    (prefx is a cop1x instruction, so can only be used if FP is
    enabled.)  */
-#define ISA_HAS_PREFETCHX      ((ISA_MIPS4                             \
-                                 || ISA_MIPS32R2                       \
-                                 || ISA_MIPS64                         \
-                                 || ISA_MIPS64R2)                      \
-                                && !TARGET_MIPS16)
+#define ISA_HAS_PREFETCHX      ISA_HAS_FP4
 
 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
    instructions.  Both require TARGET_HARD_FLOAT, and trunc.w.d

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index d3ad83cf96bd12d43cfbac54c2ebb1b4b7aed366..1bd1ec5e2cc3411890a47ba769d17721ba8bcdc6 100644 (file)
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -4440,7 +4440,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
        (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
                          (match_operand:P 2 "register_operand" "d"))))]
-  "ISA_HAS_FP4"
+  "ISA_HAS_LXC1_SXC1"
   "<ANYF:loadx>\t%0,%1(%2)"
   [(set_attr "type" "fpidxload")
    (set_attr "mode" "<ANYF:UNITMODE>")])
@@ -4449,7 +4449,7 @@
   [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
                          (match_operand:P 2 "register_operand" "d")))
        (match_operand:ANYF 0 "register_operand" "f"))]
-  "ISA_HAS_FP4"
+  "ISA_HAS_LXC1_SXC1"
   "<ANYF:storex>\t%0,%1(%2)"
   [(set_attr "type" "fpidxstore")
    (set_attr "mode" "<ANYF:UNITMODE>")])