--- /dev/null
+From 6a2a2f45560a9cb7bc49820883b042e44f83726c Mon Sep 17 00:00:00 2001
+From: Takashi Sakamoto <o-takashi@sakamocchi.jp>
+Date: Tue, 3 Jan 2017 11:58:33 +0900
+Subject: ALSA: firewire-tascam: Fix to handle error from initialization of stream data
+
+From: Takashi Sakamoto <o-takashi@sakamocchi.jp>
+
+commit 6a2a2f45560a9cb7bc49820883b042e44f83726c upstream.
+
+This module has a bug not to return error code in a case that data
+structure for transmitted packets fails to be initialized.
+
+This commit fixes the bug.
+
+Fixes: 35efa5c489de ("ALSA: firewire-tascam: add streaming functionality")
+Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
+Signed-off-by: Takashi Iwai <tiwai@suse.de>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ sound/firewire/tascam/tascam-stream.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/sound/firewire/tascam/tascam-stream.c
++++ b/sound/firewire/tascam/tascam-stream.c
+@@ -343,7 +343,7 @@ int snd_tscm_stream_init_duplex(struct s
+ if (err < 0)
+ amdtp_stream_destroy(&tscm->rx_stream);
+
+- return 0;
++ return err;
+ }
+
+ /* At bus reset, streaming is stopped and some registers are clear. */
--- /dev/null
+From 9388093db44356af911adf3d355b7544a13a63cd Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+Date: Tue, 22 Nov 2016 12:33:11 +0100
+Subject: ARM: 8631/1: clkdev: Detect errors in clk_hw_register_clkdev() for mass registration
+
+From: Geert Uytterhoeven <geert@linux-m68k.org>
+
+commit 9388093db44356af911adf3d355b7544a13a63cd upstream.
+
+Unlike clk_register_clkdev(), clk_hw_register_clkdev() doesn't check for
+passed error objects from a previous registration call. Hence the caller
+of clk_hw_register_*() has to check for errors before calling
+clk_hw_register_clkdev*().
+
+Make clk_hw_register_clkdev() more similar to clk_register_clkdev() by
+adding this error check, removing the burden from callers that do mass
+registration.
+
+Fixes: e4f1b49bda6d6aa2 ("clkdev: Add clk_hw based registration APIs")
+Fixes: 944b9a41e004534f ("clk: ls1x: Migrate to clk_hw based OF and registration APIs")
+Fixes: 44ce9a9ae977736f ("MIPS: TXx9: Convert to Common Clock Framework")
+Fixes: f48d947a162dfa9d ("clk: clps711x: Migrate to clk_hw based OF and registration APIs")
+Fixes: b4626a7f489238a5 ("CLK: Add Loongson1C clock support")
+Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/clkdev.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/clk/clkdev.c
++++ b/drivers/clk/clkdev.c
+@@ -448,12 +448,20 @@ EXPORT_SYMBOL(clk_register_clkdev);
+ *
+ * con_id or dev_id may be NULL as a wildcard, just as in the rest of
+ * clkdev.
++ *
++ * To make things easier for mass registration, we detect error clk_hws
++ * from a previous clk_hw_register_*() call, and return the error code for
++ * those. This is to permit this function to be called immediately
++ * after clk_hw_register_*().
+ */
+ int clk_hw_register_clkdev(struct clk_hw *hw, const char *con_id,
+ const char *dev_id)
+ {
+ struct clk_lookup *cl;
+
++ if (IS_ERR(hw))
++ return PTR_ERR(hw);
++
+ /*
+ * Since dev_id can be NULL, and NULL is handled specially, we must
+ * pass it as either a NULL format string, or with "%s".
--- /dev/null
+From f86a2c875fd146d9b82c8fdd86d31084507bcf4c Mon Sep 17 00:00:00 2001
+From: Grygorii Strashko <grygorii.strashko@ti.com>
+Date: Mon, 5 Dec 2016 09:27:44 +0530
+Subject: ARM: omap2+: am437x: rollback to use omap3_gptimer_timer_init()
+
+From: Grygorii Strashko <grygorii.strashko@ti.com>
+
+commit f86a2c875fd146d9b82c8fdd86d31084507bcf4c upstream.
+
+The commit 55ee7017ee31 ("arm: omap2: board-generic: use
+omap4_local_timer_init for AM437x") unintentionally changes the
+clocksource devices for AM437x from OMAP GP Timer to SyncTimer32K.
+
+Unfortunately, the SyncTimer32K is starving from frequency deviation
+as mentioned in commit 5b5c01359152 ("ARM: OMAP2+: AM43x: Use gptimer
+as clocksource") and, as reported by Franklin [1], even its monotonic
+nature is under question (most probably there is a HW issue, but it's
+still under investigation).
+
+Taking into account above facts It's reasonable to rollback to the use
+of omap3_gptimer_timer_init().
+
+[1] http://www.spinics.net/lists/linux-omap/msg127425.html
+
+Fixes: 55ee7017ee31 ("arm: omap2: board-generic: use
+omap4_local_timer_init for AM437x")
+Reported-by: Cooper Jr., Franklin <fcooper@ti.com>
+Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
+Signed-off-by: Keerthy <j-keerthy@ti.com>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/board-generic.c | 2 +-
+ arch/arm/mach-omap2/timer.c | 9 +++++----
+ 2 files changed, 6 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/mach-omap2/board-generic.c
++++ b/arch/arm/mach-omap2/board-generic.c
+@@ -306,7 +306,7 @@ DT_MACHINE_START(AM43_DT, "Generic AM43
+ .init_late = am43xx_init_late,
+ .init_irq = omap_gic_of_init,
+ .init_machine = omap_generic_init,
+- .init_time = omap4_local_timer_init,
++ .init_time = omap3_gptimer_timer_init,
+ .dt_compat = am43_boards_compat,
+ .restart = omap44xx_restart,
+ MACHINE_END
+--- a/arch/arm/mach-omap2/timer.c
++++ b/arch/arm/mach-omap2/timer.c
+@@ -510,18 +510,19 @@ void __init omap3_secure_sync32k_timer_i
+ }
+ #endif /* CONFIG_ARCH_OMAP3 */
+
+-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
++#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
++ defined(CONFIG_SOC_AM43XX)
+ void __init omap3_gptimer_timer_init(void)
+ {
+ __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
+ 1, "timer_sys_ck", "ti,timer-alwon", true);
+-
+- clocksource_probe();
++ if (of_have_populated_dt())
++ clocksource_probe();
+ }
+ #endif
+
+ #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+- defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX)
++ defined(CONFIG_SOC_DRA7XX)
+ static void __init omap4_sync32k_timer_init(void)
+ {
+ __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
--- /dev/null
+From cbf2642872333547b56b8c4d943f5ed04ac9a4ee Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 7 Nov 2016 16:50:11 -0700
+Subject: ARM: OMAP4+: Fix bad fallthrough for cpuidle
+
+From: Tony Lindgren <tony@atomide.com>
+
+commit cbf2642872333547b56b8c4d943f5ed04ac9a4ee upstream.
+
+We don't want to fall through to a bunch of errors for retention
+if PM_OMAP4_CPU_OSWR_DISABLE is not configured for a SoC.
+
+Fixes: 6099dd37c669 ("ARM: OMAP5 / DRA7: Enable CPU RET on suspend")
+Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/omap-mpuss-lowpower.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
++++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+@@ -245,10 +245,9 @@ int omap4_enter_lowpower(unsigned int cp
+ save_state = 1;
+ break;
+ case PWRDM_POWER_RET:
+- if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) {
++ if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
+ save_state = 0;
+- break;
+- }
++ break;
+ default:
+ /*
+ * CPUx CSWR is invalid hardware state. Also CPUx OSWR
--- /dev/null
+From da6d5993bf951846956903bee4f0eafd918250db Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 7 Nov 2016 16:50:10 -0700
+Subject: ARM: OMAP5: Fix build for PM code
+
+From: Tony Lindgren <tony@atomide.com>
+
+commit da6d5993bf951846956903bee4f0eafd918250db upstream.
+
+It's CONFIG_SOC_OMAP5, not CONFIG_ARCH_OMAP5. Looks like make randconfig
+builds have not hit this one yet.
+
+Fixes: b3bf289c1c45 ("ARM: OMAP2+: Fix build with CONFIG_SMP and CONFIG_PM is not set")
+Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-omap2/Makefile
++++ b/arch/arm/mach-omap2/Makefile
+@@ -80,7 +80,7 @@ endif
+ # Power Management
+ omap-4-5-pm-common = omap-mpuss-lowpower.o
+ obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-pm-common)
+-obj-$(CONFIG_ARCH_OMAP5) += $(omap-4-5-pm-common)
++obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-pm-common)
+ obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
+
+ ifeq ($(CONFIG_PM),y)
--- /dev/null
+From 8a8be46afeaa47aed1debe7e9b18152f9826a6b7 Mon Sep 17 00:00:00 2001
+From: Tony Lindgren <tony@atomide.com>
+Date: Mon, 7 Nov 2016 16:50:11 -0700
+Subject: ARM: OMAP5: Fix mpuss_early_init
+
+From: Tony Lindgren <tony@atomide.com>
+
+commit 8a8be46afeaa47aed1debe7e9b18152f9826a6b7 upstream.
+
+We need to properly initialize mpuss also on omap5 like we do on omap4.
+Otherwise we run into similar kexec problems like we had on omap4 when
+trying to kexec from a kernel with PM initialized.
+
+Fixes: 0573b957fc21 ("ARM: OMAP4+: Prevent CPU1 related hang with kexec")
+Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
+Signed-off-by: Tony Lindgren <tony@atomide.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-omap2/common.h | 38 ++++++++++++++++++++++--------
+ arch/arm/mach-omap2/io.c | 3 +-
+ arch/arm/mach-omap2/omap-mpuss-lowpower.c | 32 +++++++++++++++++++------
+ arch/arm/mach-omap2/omap4-sar-layout.h | 2 +
+ 4 files changed, 58 insertions(+), 17 deletions(-)
+
+--- a/arch/arm/mach-omap2/common.h
++++ b/arch/arm/mach-omap2/common.h
+@@ -262,8 +262,6 @@ extern void __iomem *omap4_get_sar_ram_b
+ extern void omap4_mpuss_early_init(void);
+ extern void omap_do_wfi(void);
+
+-extern void omap4_secondary_startup(void);
+-extern void omap4460_secondary_startup(void);
+
+ #ifdef CONFIG_SMP
+ /* Needed for secondary core boot */
+@@ -275,16 +273,11 @@ extern void omap4_cpu_die(unsigned int c
+ extern int omap4_cpu_kill(unsigned int cpu);
+
+ extern const struct smp_operations omap4_smp_ops;
+-
+-extern void omap5_secondary_startup(void);
+-extern void omap5_secondary_hyp_startup(void);
+ #endif
+
+ #if defined(CONFIG_SMP) && defined(CONFIG_PM)
+ extern int omap4_mpuss_init(void);
+ extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+-extern int omap4_finish_suspend(unsigned long cpu_state);
+-extern void omap4_cpu_resume(void);
+ extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+ #else
+ static inline int omap4_enter_lowpower(unsigned int cpu,
+@@ -305,14 +298,41 @@ static inline int omap4_mpuss_init(void)
+ return 0;
+ }
+
++#endif
++
++#ifdef CONFIG_ARCH_OMAP4
++void omap4_secondary_startup(void);
++void omap4460_secondary_startup(void);
++int omap4_finish_suspend(unsigned long cpu_state);
++void omap4_cpu_resume(void);
++#else
++static inline void omap4_secondary_startup(void)
++{
++}
++
++static inline void omap4460_secondary_startup(void)
++{
++}
+ static inline int omap4_finish_suspend(unsigned long cpu_state)
+ {
+ return 0;
+ }
+-
+ static inline void omap4_cpu_resume(void)
+-{}
++{
++}
++#endif
+
++#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
++void omap5_secondary_startup(void);
++void omap5_secondary_hyp_startup(void);
++#else
++static inline void omap5_secondary_startup(void)
++{
++}
++
++static inline void omap5_secondary_hyp_startup(void)
++{
++}
+ #endif
+
+ void pdata_quirks_init(const struct of_device_id *);
+--- a/arch/arm/mach-omap2/io.c
++++ b/arch/arm/mach-omap2/io.c
+@@ -717,10 +717,11 @@ void __init omap5_init_early(void)
+ OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
+ omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap2_control_base_init();
+- omap4_pm_init_early();
+ omap2_prcm_base_init();
+ omap5xxx_check_revision();
+ omap4_sar_ram_init();
++ omap4_mpuss_early_init();
++ omap4_pm_init_early();
+ omap54xx_voltagedomains_init();
+ omap54xx_powerdomains_init();
+ omap54xx_clockdomains_init();
+--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
++++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+@@ -48,6 +48,7 @@
+ #include <asm/smp_scu.h>
+ #include <asm/pgalloc.h>
+ #include <asm/suspend.h>
++#include <asm/virt.h>
+ #include <asm/hardware/cache-l2x0.h>
+
+ #include "soc.h"
+@@ -371,8 +372,12 @@ int __init omap4_mpuss_init(void)
+ pm_info = &per_cpu(omap4_pm_info, 0x0);
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+- pm_info->wkup_sar_addr = sar_base +
+- CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
++ if (cpu_is_omap44xx())
++ pm_info->wkup_sar_addr = sar_base +
++ CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
++ else
++ pm_info->wkup_sar_addr = sar_base +
++ OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ }
+ pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
+@@ -391,8 +396,12 @@ int __init omap4_mpuss_init(void)
+ pm_info = &per_cpu(omap4_pm_info, 0x1);
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+- pm_info->wkup_sar_addr = sar_base +
+- CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
++ if (cpu_is_omap44xx())
++ pm_info->wkup_sar_addr = sar_base +
++ CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
++ else
++ pm_info->wkup_sar_addr = sar_base +
++ OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ }
+
+@@ -453,15 +462,24 @@ void __init omap4_mpuss_early_init(void)
+ {
+ unsigned long startup_pa;
+
+- if (!cpu_is_omap44xx())
++ if (!(cpu_is_omap44xx() || soc_is_omap54xx()))
+ return;
+
+ sar_base = omap4_get_sar_ram_base();
+
+ if (cpu_is_omap443x())
+ startup_pa = virt_to_phys(omap4_secondary_startup);
+- else
++ else if (cpu_is_omap446x())
+ startup_pa = virt_to_phys(omap4460_secondary_startup);
++ else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
++ startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
++ else
++ startup_pa = virt_to_phys(omap5_secondary_startup);
+
+- writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
++ if (cpu_is_omap44xx())
++ writel_relaxed(startup_pa, sar_base +
++ CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
++ else
++ writel_relaxed(startup_pa, sar_base +
++ OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
+ }
+--- a/arch/arm/mach-omap2/omap4-sar-layout.h
++++ b/arch/arm/mach-omap2/omap4-sar-layout.h
+@@ -31,6 +31,8 @@
+ /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+ #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
+ #define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
++#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xe00
++#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xe04
+
+ #define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
+ #define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
--- /dev/null
+From e413bd33ac44b6d0bebc0ef2ac19cbe7558a7303 Mon Sep 17 00:00:00 2001
+From: Robert Jarzmik <robert.jarzmik@free.fr>
+Date: Mon, 26 Sep 2016 09:21:51 +0200
+Subject: ARM: pxa: fix pxa25x interrupt init
+
+From: Robert Jarzmik <robert.jarzmik@free.fr>
+
+commit e413bd33ac44b6d0bebc0ef2ac19cbe7558a7303 upstream.
+
+In the device-tree case, the root interrupt controller cannot be
+accessed through the 6th coprocessor, contrary to pxa27x and pxa3xx
+architectures.
+
+Fix it to behave as in non-devicetree builds.
+
+Fixes: 32f17997c130 ("ARM: pxa: remove irq init from dt machines")
+Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-pxa/pxa25x.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-pxa/pxa25x.c
++++ b/arch/arm/mach-pxa/pxa25x.c
+@@ -156,7 +156,7 @@ static int __init __init
+ pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent)
+ {
+ pxa_dt_irq_init(pxa25x_set_wake);
+- set_handle_irq(ichp_handle_irq);
++ set_handle_irq(icip_handle_irq);
+
+ return 0;
+ }
--- /dev/null
+From 206787737e308bb447d18adef7da7749188212f5 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <narmstrong@baylibre.com>
+Date: Wed, 7 Sep 2016 10:18:42 +0200
+Subject: ARM: qcom_defconfig: Fix MDM9515 LCC and GCC config
+
+From: Neil Armstrong <narmstrong@baylibre.com>
+
+commit 206787737e308bb447d18adef7da7749188212f5 upstream.
+
+Correct prefix is MDM instead of MSM.
+
+Fixes: 8aa788d3e59a ("ARM: configs: qualcomm: Add MDM9615 missing defconfigs")
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
+Signed-off-by: Andy Gross <andy.gross@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/configs/qcom_defconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/configs/qcom_defconfig
++++ b/arch/arm/configs/qcom_defconfig
+@@ -162,8 +162,8 @@ CONFIG_APQ_MMCC_8084=y
+ CONFIG_IPQ_LCC_806X=y
+ CONFIG_MSM_GCC_8660=y
+ CONFIG_MSM_LCC_8960=y
+-CONFIG_MSM_GCC_9615=y
+-CONFIG_MSM_LCC_9615=y
++CONFIG_MDM_GCC_9615=y
++CONFIG_MDM_LCC_9615=y
+ CONFIG_MSM_MMCC_8960=y
+ CONFIG_MSM_MMCC_8974=y
+ CONFIG_HWSPINLOCK_QCOM=y
--- /dev/null
+From 7a3cc2a7b2c723aa552028f4e66841cec183756d Mon Sep 17 00:00:00 2001
+From: Kyle Roeschley <kyle.roeschley@ni.com>
+Date: Mon, 31 Oct 2016 11:26:17 -0500
+Subject: ARM: zynq: Reserve correct amount of non-DMA RAM
+
+From: Kyle Roeschley <kyle.roeschley@ni.com>
+
+commit 7a3cc2a7b2c723aa552028f4e66841cec183756d upstream.
+
+On Zynq, we haven't been reserving the correct amount of DMA-incapable
+RAM to keep DMA away from it (per the Zynq TRM Section 4.1, it should be
+the first 512k). In older kernels, this was masked by the
+memblock_reserve call in arm_memblock_init(). Now, reserve the correct
+amount excplicitly rather than relying on swapper_pg_dir, which is an
+address and not a size anyway.
+
+Fixes: 46f5b96 ("ARM: zynq: Reserve not DMAable space in front of the kernel")
+Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com>
+Tested-by: Nathan Rossi <nathan@nathanrossi.com>
+Signed-off-by: Michal Simek <michal.simek@xilinx.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm/mach-zynq/common.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/mach-zynq/common.c
++++ b/arch/arm/mach-zynq/common.c
+@@ -59,7 +59,7 @@ void __iomem *zynq_scu_base;
+ static void __init zynq_memory_init(void)
+ {
+ if (!__pa(PAGE_OFFSET))
+- memblock_reserve(__pa(PAGE_OFFSET), __pa(swapper_pg_dir));
++ memblock_reserve(__pa(PAGE_OFFSET), 0x80000);
+ }
+
+ static struct platform_device zynq_cpuidle_device = {
--- /dev/null
+From 4f24450c6e580ac8591942c8bf65355a06b44635 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@suse.de>
+Date: Mon, 24 Oct 2016 17:09:50 +0200
+Subject: ARM64: dts: bcm2835: Fix bcm2837 compatible string
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Andreas Färber <afaerber@suse.de>
+
+commit 4f24450c6e580ac8591942c8bf65355a06b44635 upstream.
+
+bcm2837-rpi-3-b.dts, its only in-tree user, was overriding it as
+"brcm,bcm2837" already.
+
+Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")
+Cc: Stephen Warren <swarren@wwwdotorg.org>
+Signed-off-by: Andreas Färber <afaerber@suse.de>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
++++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
+@@ -1,7 +1,7 @@
+ #include "bcm283x.dtsi"
+
+ / {
+- compatible = "brcm,bcm2836";
++ compatible = "brcm,bcm2837";
+
+ soc {
+ ranges = <0x7e000000 0x3f000000 0x1000000>,
--- /dev/null
+From a44e87b47148c6ee6b78509f47e6a15c0fae890a Mon Sep 17 00:00:00 2001
+From: Andrea Merello <andrea.merello@gmail.com>
+Date: Fri, 11 Nov 2016 09:38:21 -0800
+Subject: ARM64: dts: bcm2837-rpi-3-b: remove incorrect pwr LED
+
+From: Andrea Merello <andrea.merello@gmail.com>
+
+commit a44e87b47148c6ee6b78509f47e6a15c0fae890a upstream.
+
+We are incorrectly defining the pwr LED, attaching it to a gpio line
+that is wired to the Wi-Fi SDIO module (which fails due to this).
+
+The actual power LED is connected to the GPIO expander, which we don't
+expose currently.
+
+Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")
+Thanks-to: Eric Anholt <eric@anholt.net> [for clarifying we can't control the LED]
+Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
+Signed-off-by: Eric Anholt <eric@anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
++++ b/arch/arm64/boot/dts/broadcom/bcm2837-rpi-3-b.dts
+@@ -15,13 +15,6 @@
+ act {
+ gpios = <&gpio 47 0>;
+ };
+-
+- pwr {
+- label = "PWR";
+- gpios = <&gpio 35 0>;
+- default-state = "keep";
+- linux,default-trigger = "default-on";
+- };
+ };
+ };
+
--- /dev/null
+From a3207d644fb89e5d7d5e01f00c04dcfc6d2d44d5 Mon Sep 17 00:00:00 2001
+From: Matthias Brugger <matthias.bgg@gmail.com>
+Date: Wed, 26 Oct 2016 16:15:00 +0200
+Subject: arm64: dts: mt8173: Fix auxadc node
+
+From: Matthias Brugger <matthias.bgg@gmail.com>
+
+commit a3207d644fb89e5d7d5e01f00c04dcfc6d2d44d5 upstream.
+
+The devicetree node for mt8173-auxadc lacks the clock and
+io-channel-cells property. This leads to a non-working driver.
+
+ mt6577-auxadc 11001000.auxadc: failed to get auxadc clock
+ mt6577-auxadc: probe of 11001000.auxadc failed with error -2
+
+Fix these fields to get the device up and running.
+
+Fixes: 748c7d4de46a ("ARM64: dts: mt8173: Add thermal/auxadc device
+nodes")
+Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+@@ -450,6 +450,9 @@
+ auxadc: auxadc@11001000 {
+ compatible = "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
++ clocks = <&pericfg CLK_PERI_AUXADC>;
++ clock-names = "main";
++ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
--- /dev/null
+From 26242b330093fd14c2e94fb6cbdf0f482ab26576 Mon Sep 17 00:00:00 2001
+From: Thomas Gleixner <tglx@linutronix.de>
+Date: Thu, 22 Dec 2016 11:14:06 +0100
+Subject: bus: arm-ccn: Prevent hotplug callback leak
+
+From: Thomas Gleixner <tglx@linutronix.de>
+
+commit 26242b330093fd14c2e94fb6cbdf0f482ab26576 upstream.
+
+In case the driver registration fails, the hotplug callback is leaked.
+
+Not fatal, because it's never invoked as there are no instances registered,
+but wrong nevertheless.
+
+Fixes: fdc15a36d84e ("bus/arm-ccn: Convert to hotplug statemachine")
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
+Cc: Mark Rutland <mark.rutland@arm.com>
+Cc: Pawel Moll <pawel.moll@arm.com>
+Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
+Cc: Peter Zijlstra <peterz@infradead.org>
+Cc: Will Deacon <will.deacon@arm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/bus/arm-ccn.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/bus/arm-ccn.c
++++ b/drivers/bus/arm-ccn.c
+@@ -1570,7 +1570,10 @@ static int __init arm_ccn_init(void)
+ for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
+ arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
+
+- return platform_driver_register(&arm_ccn_driver);
++ ret = platform_driver_register(&arm_ccn_driver);
++ if (ret)
++ cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
++ return ret;
+ }
+
+ static void __exit arm_ccn_exit(void)
--- /dev/null
+From 1ebb71143758f45dc0fa76e2f48429e13b16d110 Mon Sep 17 00:00:00 2001
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Date: Fri, 6 Jan 2017 15:33:36 +0100
+Subject: HID: hid-cypress: validate length of report
+
+From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+commit 1ebb71143758f45dc0fa76e2f48429e13b16d110 upstream.
+
+Make sure we have enough of a report structure to validate before
+looking at it.
+
+Reported-by: Benoit Camredon <benoit.camredon@airbus.com>
+Tested-by: Benoit Camredon <benoit.camredon@airbus.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Jiri Kosina <jkosina@suse.cz>
+
+---
+ drivers/hid/hid-cypress.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/hid/hid-cypress.c
++++ b/drivers/hid/hid-cypress.c
+@@ -39,6 +39,9 @@ static __u8 *cp_report_fixup(struct hid_
+ if (!(quirks & CP_RDESC_SWAPPED_MIN_MAX))
+ return rdesc;
+
++ if (*rsize < 4)
++ return rdesc;
++
+ for (i = 0; i < *rsize - 4; i++)
+ if (rdesc[i] == 0x29 && rdesc[i + 2] == 0x19) {
+ rdesc[i] = 0x19;
--- /dev/null
+From 8ae679c4bc2ea2d16d92620da8e3e9332fa4039f Mon Sep 17 00:00:00 2001
+From: Larry Finger <Larry.Finger@lwfinger.net>
+Date: Thu, 22 Dec 2016 21:06:53 -0600
+Subject: powerpc: Fix build warning on 32-bit PPC
+
+From: Larry Finger <Larry.Finger@lwfinger.net>
+
+commit 8ae679c4bc2ea2d16d92620da8e3e9332fa4039f upstream.
+
+I am getting the following warning when I build kernel 4.9-git on my
+PowerBook G4 with a 32-bit PPC processor:
+
+ AS arch/powerpc/kernel/misc_32.o
+ arch/powerpc/kernel/misc_32.S:299:7: warning: "CONFIG_FSL_BOOKE" is not defined [-Wundef]
+
+This problem is evident after commit 989cea5c14be ("kbuild: prevent
+lib-ksyms.o rebuilds"); however, this change in kbuild only exposes an
+error that has been in the code since 2005 when this source file was
+created. That was with commit 9994a33865f4 ("powerpc: Introduce
+entry_{32,64}.S, misc_{32,64}.S, systbl.S").
+
+The offending line does not make a lot of sense. This error does not
+seem to cause any errors in the executable, thus I am not recommending
+that it be applied to any stable versions.
+
+Thanks to Nicholas Piggin for suggesting this solution.
+
+Fixes: 9994a33865f4 ("powerpc: Introduce entry_{32,64}.S, misc_{32,64}.S, systbl.S")
+Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
+Cc: Nicholas Piggin <npiggin@gmail.com>
+Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
+Cc: Paul Mackerras <paulus@samba.org>
+Cc: Michael Ellerman <mpe@ellerman.id.au>
+Cc: linuxppc-dev@lists.ozlabs.org
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ arch/powerpc/kernel/misc_32.S | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/powerpc/kernel/misc_32.S
++++ b/arch/powerpc/kernel/misc_32.S
+@@ -296,7 +296,7 @@ _GLOBAL(flush_instruction_cache)
+ lis r3, KERNELBASE@h
+ iccci 0,r3
+ #endif
+-#elif CONFIG_FSL_BOOKE
++#elif defined(CONFIG_FSL_BOOKE)
+ BEGIN_FTR_SECTION
+ mfspr r3,SPRN_L1CSR0
+ ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
net-mlx5e-remove-warn_once-from-adaptive-moderation-code.patch
net-ipv4-fix-multipath-selection-with-vrf.patch
net-vrf-do-not-allow-table-id-0.patch
+hid-hid-cypress-validate-length-of-report.patch
+alsa-firewire-tascam-fix-to-handle-error-from-initialization-of-stream-data.patch
+powerpc-fix-build-warning-on-32-bit-ppc.patch
+tools-virtio-fix-read_once.patch
+arm64-dts-mt8173-fix-auxadc-node.patch
+arm64-dts-bcm2837-rpi-3-b-remove-incorrect-pwr-led.patch
+arm64-dts-bcm2835-fix-bcm2837-compatible-string.patch
+arm-pxa-fix-pxa25x-interrupt-init.patch
+arm-zynq-reserve-correct-amount-of-non-dma-ram.patch
+arm-qcom_defconfig-fix-mdm9515-lcc-and-gcc-config.patch
+svcrdma-clear-xpt_bc_xps-in-xprt_setup_rdma_bc-error-exit-arm.patch
+bus-arm-ccn-prevent-hotplug-callback-leak.patch
+arm-omap5-fix-mpuss_early_init.patch
+arm-omap5-fix-build-for-pm-code.patch
+arm-omap4-fix-bad-fallthrough-for-cpuidle.patch
+arm-8631-1-clkdev-detect-errors-in-clk_hw_register_clkdev-for-mass-registration.patch
+arm-omap2-am437x-rollback-to-use-omap3_gptimer_timer_init.patch
+spi-mvebu-fix-baudrate-calculation-for-armada-variant.patch
--- /dev/null
+From 7243e0b20729d372e97763617a7a9c89f29b33e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <uwe@kleine-koenig.org>
+Date: Thu, 8 Dec 2016 17:37:08 +0100
+Subject: spi: mvebu: fix baudrate calculation for armada variant
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Uwe Kleine-König <uwe@kleine-koenig.org>
+
+commit 7243e0b20729d372e97763617a7a9c89f29b33e1 upstream.
+
+The calculation of SPR and SPPR doesn't round correctly at several
+places which might result in baud rates that are too big. For example
+with tclk_hz = 250000001 and target rate 25000000 it determined a
+divider of 10 which is wrong.
+
+Instead of fixing all the corner cases replace the calculation by an
+algorithm without a loop which should even be quicker to execute apart
+from being correct.
+
+Fixes: df59fa7f4bca ("spi: orion: support armada extended baud rates")
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/spi/spi-orion.c | 83 +++++++++++++++++++++++++++++++-----------------
+ 1 file changed, 54 insertions(+), 29 deletions(-)
+
+--- a/drivers/spi/spi-orion.c
++++ b/drivers/spi/spi-orion.c
+@@ -138,37 +138,62 @@ static int orion_spi_baudrate_set(struct
+ tclk_hz = clk_get_rate(orion_spi->clk);
+
+ if (devdata->typ == ARMADA_SPI) {
+- unsigned int clk, spr, sppr, sppr2, err;
+- unsigned int best_spr, best_sppr, best_err;
+-
+- best_err = speed;
+- best_spr = 0;
+- best_sppr = 0;
+-
+- /* Iterate over the valid range looking for best fit */
+- for (sppr = 0; sppr < 8; sppr++) {
+- sppr2 = 0x1 << sppr;
+-
+- spr = tclk_hz / sppr2;
+- spr = DIV_ROUND_UP(spr, speed);
+- if ((spr == 0) || (spr > 15))
+- continue;
+-
+- clk = tclk_hz / (spr * sppr2);
+- err = speed - clk;
+-
+- if (err < best_err) {
+- best_spr = spr;
+- best_sppr = sppr;
+- best_err = err;
+- }
++ /*
++ * Given the core_clk (tclk_hz) and the target rate (speed) we
++ * determine the best values for SPR (in [0 .. 15]) and SPPR (in
++ * [0..7]) such that
++ *
++ * core_clk / (SPR * 2 ** SPPR)
++ *
++ * is as big as possible but not bigger than speed.
++ */
++
++ /* best integer divider: */
++ unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
++ unsigned spr, sppr;
++
++ if (divider < 16) {
++ /* This is the easy case, divider is less than 16 */
++ spr = divider;
++ sppr = 0;
++
++ } else {
++ unsigned two_pow_sppr;
++ /*
++ * Find the highest bit set in divider. This and the
++ * three next bits define SPR (apart from rounding).
++ * SPPR is then the number of zero bits that must be
++ * appended:
++ */
++ sppr = fls(divider) - 4;
++
++ /*
++ * As SPR only has 4 bits, we have to round divider up
++ * to the next multiple of 2 ** sppr.
++ */
++ two_pow_sppr = 1 << sppr;
++ divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
++
++ /*
++ * recalculate sppr as rounding up divider might have
++ * increased it enough to change the position of the
++ * highest set bit. In this case the bit that now
++ * doesn't make it into SPR is 0, so there is no need to
++ * round again.
++ */
++ sppr = fls(divider) - 4;
++ spr = divider >> sppr;
++
++ /*
++ * Now do range checking. SPR is constructed to have a
++ * width of 4 bits, so this is fine for sure. So we
++ * still need to check for sppr to fit into 3 bits:
++ */
++ if (sppr > 7)
++ return -EINVAL;
+ }
+
+- if ((best_sppr == 0) && (best_spr == 0))
+- return -EINVAL;
+-
+- prescale = ((best_sppr & 0x6) << 5) |
+- ((best_sppr & 0x1) << 4) | best_spr;
++ prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
+ } else {
+ /*
+ * the supported rates are: 4,6,8...30
--- /dev/null
+From 1b9f700b8cfc31089e2dfa5d0905c52fd4529b50 Mon Sep 17 00:00:00 2001
+From: Chuck Lever <chuck.lever@oracle.com>
+Date: Tue, 29 Nov 2016 11:04:26 -0500
+Subject: svcrdma: Clear xpt_bc_xps in xprt_setup_rdma_bc() error exit arm
+
+From: Chuck Lever <chuck.lever@oracle.com>
+
+commit 1b9f700b8cfc31089e2dfa5d0905c52fd4529b50 upstream.
+
+Logic copied from xs_setup_bc_tcp().
+
+Fixes: 39a9beab5acb ('rpc: share one xps between all backchannels')
+Signed-off-by: Chuck Lever <chuck.lever@oracle.com>
+Signed-off-by: J. Bruce Fields <bfields@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ net/sunrpc/xprtrdma/svc_rdma_backchannel.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/net/sunrpc/xprtrdma/svc_rdma_backchannel.c
++++ b/net/sunrpc/xprtrdma/svc_rdma_backchannel.c
+@@ -359,6 +359,7 @@ xprt_setup_rdma_bc(struct xprt_create *a
+ out_fail:
+ xprt_rdma_free_addresses(xprt);
+ args->bc_xprt->xpt_bc_xprt = NULL;
++ args->bc_xprt->xpt_bc_xps = NULL;
+ xprt_put(xprt);
+ xprt_free(xprt);
+ return ERR_PTR(-EINVAL);
--- /dev/null
+From 5da889c795b1fbefc9d8f058b54717ab8ab17891 Mon Sep 17 00:00:00 2001
+From: Mark Rutland <mark.rutland@arm.com>
+Date: Thu, 24 Nov 2016 10:25:12 +0000
+Subject: tools/virtio: fix READ_ONCE()
+
+From: Mark Rutland <mark.rutland@arm.com>
+
+commit 5da889c795b1fbefc9d8f058b54717ab8ab17891 upstream.
+
+The virtio tools implementation of READ_ONCE() has a single parameter called
+'var', but erroneously refers to 'val' for its cast, and thus won't work unless
+there's a variable of the correct type that happens to be called 'var'.
+
+Fix this with s/var/val/, making READ_ONCE() work as expected regardless.
+
+Fixes: a7c490333df3cff5 ("tools/virtio: use virt_xxx barriers")
+Signed-off-by: Mark Rutland <mark.rutland@arm.com>
+Cc: Jason Wang <jasowang@redhat.com>
+Cc: Michael S. Tsirkin <mst@redhat.com>
+Cc: linux-kernel@vger.kernel.org
+Cc: virtualization@lists.linux-foundation.org
+Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
+Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
+Reviewed-by: Jason Wang <jasowang@redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ tools/virtio/linux/compiler.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/tools/virtio/linux/compiler.h
++++ b/tools/virtio/linux/compiler.h
+@@ -4,6 +4,6 @@
+ #define WRITE_ONCE(var, val) \
+ (*((volatile typeof(val) *)(&(var))) = (val))
+
+-#define READ_ONCE(var) (*((volatile typeof(val) *)(&(var))))
++#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
+
+ #endif