--- /dev/null
+From f4ea67a722e8c9e1fb8109adebb9fb881ff0793a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= <rkrcmar@ventanamicro.com>
+Date: Fri, 25 Jul 2025 18:54:10 +0200
+Subject: riscv: use lw when reading int cpu in asm_per_cpu
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Radim Krčmář <rkrcmar@ventanamicro.com>
+
+commit f4ea67a722e8c9e1fb8109adebb9fb881ff0793a upstream.
+
+REG_L is wrong, because thread_info.cpu is 32-bit, not xlen-bit wide.
+The struct currently has a hole after cpu, so little endian accesses
+seemed fine.
+
+Fixes: be97d0db5f44 ("riscv: VMAP_STACK overflow detection thread-safe")
+Cc: stable@vger.kernel.org
+Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
+Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com>
+Link: https://lore.kernel.org/r/20250725165410.2896641-5-rkrcmar@ventanamicro.com
+Signed-off-by: Paul Walmsley <pjw@kernel.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ arch/riscv/include/asm/asm.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/riscv/include/asm/asm.h
++++ b/arch/riscv/include/asm/asm.h
+@@ -90,7 +90,7 @@
+ #endif
+
+ .macro asm_per_cpu dst sym tmp
+- REG_L \tmp, TASK_TI_CPU_NUM(tp)
++ lw \tmp, TASK_TI_CPU_NUM(tp)
+ slli \tmp, \tmp, PER_CPU_OFFSET_SHIFT
+ la \dst, __per_cpu_offset
+ add \dst, \dst, \tmp