arm64: dts: renesas: r9a09g057: Add ICU node

Add node for the Interrupt Control Unit IP found on the Renesas
RZ/V2H(P) SoC, and modify the pinctrl node as its interrupt parent
is the ICU node.

Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/all/20241009230817.798582-4-fabrizio.castro.jz@renesas.com

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 1ad5a1b6917fee3e11203a5a62350d8c824bc73a..abcdef3ba5bc19e95dfc7a4042a82379821efcbe 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -90,6 +90,95 @@
                #size-cells = <2>;
                ranges;
 
+               icu: interrupt-controller@10400000 {
+                       compatible = "renesas,r9a09g057-icu";
+                       reg = <0 0x10400000 0 0x10000>;
+                       #interrupt-cells = <2>;
+                       #address-cells = <0>;
+                       interrupt-controller;
+                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "nmi",
+                                         "port_irq0", "port_irq1", "port_irq2",
+                                         "port_irq3", "port_irq4", "port_irq5",
+                                         "port_irq6", "port_irq7", "port_irq8",
+                                         "port_irq9", "port_irq10", "port_irq11",
+                                         "port_irq12", "port_irq13", "port_irq14",
+                                         "port_irq15",
+                                         "tint0", "tint1", "tint2", "tint3",
+                                         "tint4", "tint5", "tint6", "tint7",
+                                         "tint8", "tint9", "tint10", "tint11",
+                                         "tint12", "tint13", "tint14", "tint15",
+                                         "tint16", "tint17", "tint18", "tint19",
+                                         "tint20", "tint21", "tint22", "tint23",
+                                         "tint24", "tint25", "tint26", "tint27",
+                                         "tint28", "tint29", "tint30", "tint31",
+                                         "int-ca55-0", "int-ca55-1",
+                                         "int-ca55-2", "int-ca55-3",
+                                         "icu-error-ca55",
+                                         "gpt-u0-gtciada", "gpt-u0-gtciadb",
+                                         "gpt-u1-gtciada", "gpt-u1-gtciadb";
+                       clocks = <&cpg CPG_MOD 0x5>;
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0x36>;
+               };
+
                pinctrl: pinctrl@10410000 {
                        compatible = "renesas,r9a09g057-pinctrl";
                        reg = <0 0x10410000 0 0x10000>;
@@ -99,6 +188,7 @@
                        gpio-ranges = <&pinctrl 0 0 96>;
                        #interrupt-cells = <2>;
                        interrupt-controller;
+                       interrupt-parent = <&icu>;
                        power-domains = <&cpg>;
                        resets = <&cpg 0xa5>, <&cpg 0xa6>;
                };