clk: imx: fracn-gppll: fix fractional part of PLL getting lost

Fractional part of PLL gets lost after re-enabling the PLL. the
MFN can NOT be automatically loaded when doing frac PLL enable/disable,
So when re-enable PLL, configure mfn explicitly.

Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240607133347.3291040-5-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 44462ab50e513c05a3a4fb5307cfb1eb393b6e6b..1becba2b62d0beb02fedcea912a073eadf14f525 100644 (file)
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -291,6 +291,10 @@ static int clk_fracn_gppll_prepare(struct clk_hw *hw)
        if (val & POWERUP_MASK)
                return 0;
 
+       if (pll->flags & CLK_FRACN_GPPLL_FRACN)
+               writel_relaxed(readl_relaxed(pll->base + PLL_NUMERATOR),
+                              pll->base + PLL_NUMERATOR);
+
        val |= CLKMUX_BYPASS;
        writel_relaxed(val, pll->base + PLL_CTRL);