RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore it
makes sense to group them into smaller chunks in form of vendor
extensions.

This patch adds provides load/store segment instructions for T-Head VECTOR
vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector
extension, but belongs to the "XTheadVector" extension. The 'th' prefix
and the "XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add test.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index d7cb1e1a4571bbe86dbe8bb77a1b211af81728a5..90ea839457aaf160396f4ec7998ab1eaa7bd1d36 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -142,3 +142,843 @@ Disassembly of section .text:
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+[      ]+[0-9a-f]+:[   ]+ecc56227[     ]+th.vsxseg8w.v[        ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+eec57227[     ]+th.vsxseg8e.v[        ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+eec57227[     ]+th.vsxseg8e.v[        ]+v4,\(a0\),v12
+[      ]+[0-9a-f]+:[   ]+ecc57227[     ]+th.vsxseg8e.v[        ]+v4,\(a0\),v12,v0.t
+[      ]+[0-9a-f]+:[   ]+33050207[     ]+th.vlseg2bff.v[       ]+v4,\(a0\)
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+[      ]+[0-9a-f]+:[   ]+33055207[     ]+th.vlseg2hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+33055207[     ]+th.vlseg2hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+31055207[     ]+th.vlseg2hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+33056207[     ]+th.vlseg2wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+33056207[     ]+th.vlseg2wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+31056207[     ]+th.vlseg2wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+23050207[     ]+th.vlseg2buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+23050207[     ]+th.vlseg2buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+21050207[     ]+th.vlseg2buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+23055207[     ]+th.vlseg2huff.v[      ]+v4,\(a0\)
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+[      ]+[0-9a-f]+:[   ]+23056207[     ]+th.vlseg2wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+23056207[     ]+th.vlseg2wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+21056207[     ]+th.vlseg2wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+23057207[     ]+th.vlseg2eff.v[       ]+v4,\(a0\)
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+[      ]+[0-9a-f]+:[   ]+21057207[     ]+th.vlseg2eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+53050207[     ]+th.vlseg3bff.v[       ]+v4,\(a0\)
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+[      ]+[0-9a-f]+:[   ]+51050207[     ]+th.vlseg3bff.v[       ]+v4,\(a0\),v0.t
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+[      ]+[0-9a-f]+:[   ]+53056207[     ]+th.vlseg3wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+53056207[     ]+th.vlseg3wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+51056207[     ]+th.vlseg3wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+43050207[     ]+th.vlseg3buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+43050207[     ]+th.vlseg3buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+41050207[     ]+th.vlseg3buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+43055207[     ]+th.vlseg3huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+43055207[     ]+th.vlseg3huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+41055207[     ]+th.vlseg3huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+43056207[     ]+th.vlseg3wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+43056207[     ]+th.vlseg3wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+41056207[     ]+th.vlseg3wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+43057207[     ]+th.vlseg3eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+43057207[     ]+th.vlseg3eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+41057207[     ]+th.vlseg3eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+73050207[     ]+th.vlseg4bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+73050207[     ]+th.vlseg4bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+71050207[     ]+th.vlseg4bff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+73055207[     ]+th.vlseg4hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+73055207[     ]+th.vlseg4hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+71055207[     ]+th.vlseg4hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+73056207[     ]+th.vlseg4wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+73056207[     ]+th.vlseg4wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+71056207[     ]+th.vlseg4wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+63050207[     ]+th.vlseg4buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+63050207[     ]+th.vlseg4buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+61050207[     ]+th.vlseg4buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+63055207[     ]+th.vlseg4huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+63055207[     ]+th.vlseg4huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+61055207[     ]+th.vlseg4huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+63056207[     ]+th.vlseg4wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+63056207[     ]+th.vlseg4wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+61056207[     ]+th.vlseg4wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+63057207[     ]+th.vlseg4eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+63057207[     ]+th.vlseg4eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+61057207[     ]+th.vlseg4eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+93050207[     ]+th.vlseg5bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+93050207[     ]+th.vlseg5bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+91050207[     ]+th.vlseg5bff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+93055207[     ]+th.vlseg5hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+93055207[     ]+th.vlseg5hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+91055207[     ]+th.vlseg5hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+93056207[     ]+th.vlseg5wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+93056207[     ]+th.vlseg5wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+91056207[     ]+th.vlseg5wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+83050207[     ]+th.vlseg5buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+83050207[     ]+th.vlseg5buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+81050207[     ]+th.vlseg5buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+83055207[     ]+th.vlseg5huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+83055207[     ]+th.vlseg5huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+81055207[     ]+th.vlseg5huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+83056207[     ]+th.vlseg5wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+83056207[     ]+th.vlseg5wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+81056207[     ]+th.vlseg5wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+83057207[     ]+th.vlseg5eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+83057207[     ]+th.vlseg5eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+81057207[     ]+th.vlseg5eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+b3050207[     ]+th.vlseg6bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b3050207[     ]+th.vlseg6bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b1050207[     ]+th.vlseg6bff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+b3055207[     ]+th.vlseg6hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b3055207[     ]+th.vlseg6hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b1055207[     ]+th.vlseg6hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+b3056207[     ]+th.vlseg6wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b3056207[     ]+th.vlseg6wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+b1056207[     ]+th.vlseg6wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+a3050207[     ]+th.vlseg6buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a3050207[     ]+th.vlseg6buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a1050207[     ]+th.vlseg6buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+a3055207[     ]+th.vlseg6huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a3055207[     ]+th.vlseg6huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a1055207[     ]+th.vlseg6huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+a3056207[     ]+th.vlseg6wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a3056207[     ]+th.vlseg6wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a1056207[     ]+th.vlseg6wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+a3057207[     ]+th.vlseg6eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a3057207[     ]+th.vlseg6eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+a1057207[     ]+th.vlseg6eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+d3050207[     ]+th.vlseg7bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d3050207[     ]+th.vlseg7bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d1050207[     ]+th.vlseg7bff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+d3055207[     ]+th.vlseg7hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d3055207[     ]+th.vlseg7hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d1055207[     ]+th.vlseg7hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+d3056207[     ]+th.vlseg7wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d3056207[     ]+th.vlseg7wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+d1056207[     ]+th.vlseg7wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+c3050207[     ]+th.vlseg7buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c3050207[     ]+th.vlseg7buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c1050207[     ]+th.vlseg7buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+c3055207[     ]+th.vlseg7huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c3055207[     ]+th.vlseg7huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c1055207[     ]+th.vlseg7huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+c3056207[     ]+th.vlseg7wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c3056207[     ]+th.vlseg7wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c1056207[     ]+th.vlseg7wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+c3057207[     ]+th.vlseg7eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c3057207[     ]+th.vlseg7eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+c1057207[     ]+th.vlseg7eff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+f3050207[     ]+th.vlseg8bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f3050207[     ]+th.vlseg8bff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f1050207[     ]+th.vlseg8bff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+f3055207[     ]+th.vlseg8hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f3055207[     ]+th.vlseg8hff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f1055207[     ]+th.vlseg8hff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+f3056207[     ]+th.vlseg8wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f3056207[     ]+th.vlseg8wff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+f1056207[     ]+th.vlseg8wff.v[       ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+e3050207[     ]+th.vlseg8buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e3050207[     ]+th.vlseg8buff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e1050207[     ]+th.vlseg8buff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+e3055207[     ]+th.vlseg8huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e3055207[     ]+th.vlseg8huff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e1055207[     ]+th.vlseg8huff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+e3056207[     ]+th.vlseg8wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e3056207[     ]+th.vlseg8wuff.v[      ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e1056207[     ]+th.vlseg8wuff.v[      ]+v4,\(a0\),v0.t
+[      ]+[0-9a-f]+:[   ]+e3057207[     ]+th.vlseg8eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e3057207[     ]+th.vlseg8eff.v[       ]+v4,\(a0\)
+[      ]+[0-9a-f]+:[   ]+e1057207[     ]+th.vlseg8eff.v[       ]+v4,\(a0\),v0.t

diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index c65e9e8790cf2cf80da7815c87551c28dc6951cc..d356c016c2fdebf12deda8a8aa47716f0cdf7151 100644 (file)
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -137,3 +137,871 @@
        th.vleff.v v4, (a0)
        th.vleff.v v4, 0(a0)
        th.vleff.v v4, (a0), v0.t
+
+       th.vlseg2b.v v4, (a0)
+       th.vlseg2b.v v4, 0(a0)
+       th.vlseg2b.v v4, (a0), v0.t
+       th.vlseg2h.v v4, (a0)
+       th.vlseg2h.v v4, 0(a0)
+       th.vlseg2h.v v4, (a0), v0.t
+       th.vlseg2w.v v4, (a0)
+       th.vlseg2w.v v4, 0(a0)
+       th.vlseg2w.v v4, (a0), v0.t
+       th.vlseg2bu.v v4, (a0)
+       th.vlseg2bu.v v4, 0(a0)
+       th.vlseg2bu.v v4, (a0), v0.t
+       th.vlseg2hu.v v4, (a0)
+       th.vlseg2hu.v v4, 0(a0)
+       th.vlseg2hu.v v4, (a0), v0.t
+       th.vlseg2wu.v v4, (a0)
+       th.vlseg2wu.v v4, 0(a0)
+       th.vlseg2wu.v v4, (a0), v0.t
+       th.vlseg2e.v v4, (a0)
+       th.vlseg2e.v v4, 0(a0)
+       th.vlseg2e.v v4, (a0), v0.t
+       th.vsseg2b.v v4, (a0)
+       th.vsseg2b.v v4, 0(a0)
+       th.vsseg2b.v v4, (a0), v0.t
+       th.vsseg2h.v v4, (a0)
+       th.vsseg2h.v v4, 0(a0)
+       th.vsseg2h.v v4, (a0), v0.t
+       th.vsseg2w.v v4, (a0)
+       th.vsseg2w.v v4, 0(a0)
+       th.vsseg2w.v v4, (a0), v0.t
+       th.vsseg2e.v v4, (a0)
+       th.vsseg2e.v v4, 0(a0)
+       th.vsseg2e.v v4, (a0), v0.t
+
+       th.vlseg3b.v v4, (a0)
+       th.vlseg3b.v v4, 0(a0)
+       th.vlseg3b.v v4, (a0), v0.t
+       th.vlseg3h.v v4, (a0)
+       th.vlseg3h.v v4, 0(a0)
+       th.vlseg3h.v v4, (a0), v0.t
+       th.vlseg3w.v v4, (a0)
+       th.vlseg3w.v v4, 0(a0)
+       th.vlseg3w.v v4, (a0), v0.t
+       th.vlseg3bu.v v4, (a0)
+       th.vlseg3bu.v v4, 0(a0)
+       th.vlseg3bu.v v4, (a0), v0.t
+       th.vlseg3hu.v v4, (a0)
+       th.vlseg3hu.v v4, 0(a0)
+       th.vlseg3hu.v v4, (a0), v0.t
+       th.vlseg3wu.v v4, (a0)
+       th.vlseg3wu.v v4, 0(a0)
+       th.vlseg3wu.v v4, (a0), v0.t
+       th.vlseg3e.v v4, (a0)
+       th.vlseg3e.v v4, 0(a0)
+       th.vlseg3e.v v4, (a0), v0.t
+       th.vsseg3b.v v4, (a0)
+       th.vsseg3b.v v4, 0(a0)
+       th.vsseg3b.v v4, (a0), v0.t
+       th.vsseg3h.v v4, (a0)
+       th.vsseg3h.v v4, 0(a0)
+       th.vsseg3h.v v4, (a0), v0.t
+       th.vsseg3w.v v4, (a0)
+       th.vsseg3w.v v4, 0(a0)
+       th.vsseg3w.v v4, (a0), v0.t
+       th.vsseg3e.v v4, (a0)
+       th.vsseg3e.v v4, 0(a0)
+       th.vsseg3e.v v4, (a0), v0.t
+
+       th.vlseg4b.v v4, (a0)
+       th.vlseg4b.v v4, 0(a0)
+       th.vlseg4b.v v4, (a0), v0.t
+       th.vlseg4h.v v4, (a0)
+       th.vlseg4h.v v4, 0(a0)
+       th.vlseg4h.v v4, (a0), v0.t
+       th.vlseg4w.v v4, (a0)
+       th.vlseg4w.v v4, 0(a0)
+       th.vlseg4w.v v4, (a0), v0.t
+       th.vlseg4bu.v v4, (a0)
+       th.vlseg4bu.v v4, 0(a0)
+       th.vlseg4bu.v v4, (a0), v0.t
+       th.vlseg4hu.v v4, (a0)
+       th.vlseg4hu.v v4, 0(a0)
+       th.vlseg4hu.v v4, (a0), v0.t
+       th.vlseg4wu.v v4, (a0)
+       th.vlseg4wu.v v4, 0(a0)
+       th.vlseg4wu.v v4, (a0), v0.t
+       th.vlseg4e.v v4, (a0)
+       th.vlseg4e.v v4, 0(a0)
+       th.vlseg4e.v v4, (a0), v0.t
+       th.vsseg4b.v v4, (a0)
+       th.vsseg4b.v v4, 0(a0)
+       th.vsseg4b.v v4, (a0), v0.t
+       th.vsseg4h.v v4, (a0)
+       th.vsseg4h.v v4, 0(a0)
+       th.vsseg4h.v v4, (a0), v0.t
+       th.vsseg4w.v v4, (a0)
+       th.vsseg4w.v v4, 0(a0)
+       th.vsseg4w.v v4, (a0), v0.t
+       th.vsseg4e.v v4, (a0)
+       th.vsseg4e.v v4, 0(a0)
+       th.vsseg4e.v v4, (a0), v0.t
+
+       th.vlseg5b.v v4, (a0)
+       th.vlseg5b.v v4, 0(a0)
+       th.vlseg5b.v v4, (a0), v0.t
+       th.vlseg5h.v v4, (a0)
+       th.vlseg5h.v v4, 0(a0)
+       th.vlseg5h.v v4, (a0), v0.t
+       th.vlseg5w.v v4, (a0)
+       th.vlseg5w.v v4, 0(a0)
+       th.vlseg5w.v v4, (a0), v0.t
+       th.vlseg5bu.v v4, (a0)
+       th.vlseg5bu.v v4, 0(a0)
+       th.vlseg5bu.v v4, (a0), v0.t
+       th.vlseg5hu.v v4, (a0)
+       th.vlseg5hu.v v4, 0(a0)
+       th.vlseg5hu.v v4, (a0), v0.t
+       th.vlseg5wu.v v4, (a0)
+       th.vlseg5wu.v v4, 0(a0)
+       th.vlseg5wu.v v4, (a0), v0.t
+       th.vlseg5e.v v4, (a0)
+       th.vlseg5e.v v4, 0(a0)
+       th.vlseg5e.v v4, (a0), v0.t
+       th.vsseg5b.v v4, (a0)
+       th.vsseg5b.v v4, 0(a0)
+       th.vsseg5b.v v4, (a0), v0.t
+       th.vsseg5h.v v4, (a0)
+       th.vsseg5h.v v4, 0(a0)
+       th.vsseg5h.v v4, (a0), v0.t
+       th.vsseg5w.v v4, (a0)
+       th.vsseg5w.v v4, 0(a0)
+       th.vsseg5w.v v4, (a0), v0.t
+       th.vsseg5e.v v4, (a0)
+       th.vsseg5e.v v4, 0(a0)
+       th.vsseg5e.v v4, (a0), v0.t
+
+       th.vlseg6b.v v4, (a0)
+       th.vlseg6b.v v4, 0(a0)
+       th.vlseg6b.v v4, (a0), v0.t
+       th.vlseg6h.v v4, (a0)
+       th.vlseg6h.v v4, 0(a0)
+       th.vlseg6h.v v4, (a0), v0.t
+       th.vlseg6w.v v4, (a0)
+       th.vlseg6w.v v4, 0(a0)
+       th.vlseg6w.v v4, (a0), v0.t
+       th.vlseg6bu.v v4, (a0)
+       th.vlseg6bu.v v4, 0(a0)
+       th.vlseg6bu.v v4, (a0), v0.t
+       th.vlseg6hu.v v4, (a0)
+       th.vlseg6hu.v v4, 0(a0)
+       th.vlseg6hu.v v4, (a0), v0.t
+       th.vlseg6wu.v v4, (a0)
+       th.vlseg6wu.v v4, 0(a0)
+       th.vlseg6wu.v v4, (a0), v0.t
+       th.vlseg6e.v v4, (a0)
+       th.vlseg6e.v v4, 0(a0)
+       th.vlseg6e.v v4, (a0), v0.t
+       th.vsseg6b.v v4, (a0)
+       th.vsseg6b.v v4, 0(a0)
+       th.vsseg6b.v v4, (a0), v0.t
+       th.vsseg6h.v v4, (a0)
+       th.vsseg6h.v v4, 0(a0)
+       th.vsseg6h.v v4, (a0), v0.t
+       th.vsseg6w.v v4, (a0)
+       th.vsseg6w.v v4, 0(a0)
+       th.vsseg6w.v v4, (a0), v0.t
+       th.vsseg6e.v v4, (a0)
+       th.vsseg6e.v v4, 0(a0)
+       th.vsseg6e.v v4, (a0), v0.t
+
+       th.vlseg7b.v v4, (a0)
+       th.vlseg7b.v v4, 0(a0)
+       th.vlseg7b.v v4, (a0), v0.t
+       th.vlseg7h.v v4, (a0)
+       th.vlseg7h.v v4, 0(a0)
+       th.vlseg7h.v v4, (a0), v0.t
+       th.vlseg7w.v v4, (a0)
+       th.vlseg7w.v v4, 0(a0)
+       th.vlseg7w.v v4, (a0), v0.t
+       th.vlseg7bu.v v4, (a0)
+       th.vlseg7bu.v v4, 0(a0)
+       th.vlseg7bu.v v4, (a0), v0.t
+       th.vlseg7hu.v v4, (a0)
+       th.vlseg7hu.v v4, 0(a0)
+       th.vlseg7hu.v v4, (a0), v0.t
+       th.vlseg7wu.v v4, (a0)
+       th.vlseg7wu.v v4, 0(a0)
+       th.vlseg7wu.v v4, (a0), v0.t
+       th.vlseg7e.v v4, (a0)
+       th.vlseg7e.v v4, 0(a0)
+       th.vlseg7e.v v4, (a0), v0.t
+       th.vsseg7b.v v4, (a0)
+       th.vsseg7b.v v4, 0(a0)
+       th.vsseg7b.v v4, (a0), v0.t
+       th.vsseg7h.v v4, (a0)
+       th.vsseg7h.v v4, 0(a0)
+       th.vsseg7h.v v4, (a0), v0.t
+       th.vsseg7w.v v4, (a0)
+       th.vsseg7w.v v4, 0(a0)
+       th.vsseg7w.v v4, (a0), v0.t
+       th.vsseg7e.v v4, (a0)
+       th.vsseg7e.v v4, 0(a0)
+       th.vsseg7e.v v4, (a0), v0.t
+
+       th.vlseg8b.v v4, (a0)
+       th.vlseg8b.v v4, 0(a0)
+       th.vlseg8b.v v4, (a0), v0.t
+       th.vlseg8h.v v4, (a0)
+       th.vlseg8h.v v4, 0(a0)
+       th.vlseg8h.v v4, (a0), v0.t
+       th.vlseg8w.v v4, (a0)
+       th.vlseg8w.v v4, 0(a0)
+       th.vlseg8w.v v4, (a0), v0.t
+       th.vlseg8bu.v v4, (a0)
+       th.vlseg8bu.v v4, 0(a0)
+       th.vlseg8bu.v v4, (a0), v0.t
+       th.vlseg8hu.v v4, (a0)
+       th.vlseg8hu.v v4, 0(a0)
+       th.vlseg8hu.v v4, (a0), v0.t
+       th.vlseg8wu.v v4, (a0)
+       th.vlseg8wu.v v4, 0(a0)
+       th.vlseg8wu.v v4, (a0), v0.t
+       th.vlseg8e.v v4, (a0)
+       th.vlseg8e.v v4, 0(a0)
+       th.vlseg8e.v v4, (a0), v0.t
+       th.vsseg8b.v v4, (a0)
+       th.vsseg8b.v v4, 0(a0)
+       th.vsseg8b.v v4, (a0), v0.t
+       th.vsseg8h.v v4, (a0)
+       th.vsseg8h.v v4, 0(a0)
+       th.vsseg8h.v v4, (a0), v0.t
+       th.vsseg8w.v v4, (a0)
+       th.vsseg8w.v v4, 0(a0)
+       th.vsseg8w.v v4, (a0), v0.t
+       th.vsseg8e.v v4, (a0)
+       th.vsseg8e.v v4, 0(a0)
+       th.vsseg8e.v v4, (a0), v0.t
+
+       th.vlsseg2b.v v4, (a0), a1
+       th.vlsseg2b.v v4, 0(a0), a1
+       th.vlsseg2b.v v4, (a0), a1, v0.t
+       th.vlsseg2h.v v4, (a0), a1
+       th.vlsseg2h.v v4, 0(a0), a1
+       th.vlsseg2h.v v4, (a0), a1, v0.t
+       th.vlsseg2w.v v4, (a0), a1
+       th.vlsseg2w.v v4, 0(a0), a1
+       th.vlsseg2w.v v4, (a0), a1, v0.t
+       th.vlsseg2bu.v v4, (a0), a1
+       th.vlsseg2bu.v v4, 0(a0), a1
+       th.vlsseg2bu.v v4, (a0), a1, v0.t
+       th.vlsseg2hu.v v4, (a0), a1
+       th.vlsseg2hu.v v4, 0(a0), a1
+       th.vlsseg2hu.v v4, (a0), a1, v0.t
+       th.vlsseg2wu.v v4, (a0), a1
+       th.vlsseg2wu.v v4, 0(a0), a1
+       th.vlsseg2wu.v v4, (a0), a1, v0.t
+       th.vlsseg2e.v v4, (a0), a1
+       th.vlsseg2e.v v4, 0(a0), a1
+       th.vlsseg2e.v v4, (a0), a1, v0.t
+       th.vssseg2b.v v4, (a0), a1
+       th.vssseg2b.v v4, 0(a0), a1
+       th.vssseg2b.v v4, (a0), a1, v0.t
+       th.vssseg2h.v v4, (a0), a1
+       th.vssseg2h.v v4, 0(a0), a1
+       th.vssseg2h.v v4, (a0), a1, v0.t
+       th.vssseg2w.v v4, (a0), a1
+       th.vssseg2w.v v4, 0(a0), a1
+       th.vssseg2w.v v4, (a0), a1, v0.t
+       th.vssseg2e.v v4, (a0), a1
+       th.vssseg2e.v v4, 0(a0), a1
+       th.vssseg2e.v v4, (a0), a1, v0.t
+
+       th.vlsseg3b.v v4, (a0), a1
+       th.vlsseg3b.v v4, 0(a0), a1
+       th.vlsseg3b.v v4, (a0), a1, v0.t
+       th.vlsseg3h.v v4, (a0), a1
+       th.vlsseg3h.v v4, 0(a0), a1
+       th.vlsseg3h.v v4, (a0), a1, v0.t
+       th.vlsseg3w.v v4, (a0), a1
+       th.vlsseg3w.v v4, 0(a0), a1
+       th.vlsseg3w.v v4, (a0), a1, v0.t
+       th.vlsseg3bu.v v4, (a0), a1
+       th.vlsseg3bu.v v4, 0(a0), a1
+       th.vlsseg3bu.v v4, (a0), a1, v0.t
+       th.vlsseg3hu.v v4, (a0), a1
+       th.vlsseg3hu.v v4, 0(a0), a1
+       th.vlsseg3hu.v v4, (a0), a1, v0.t
+       th.vlsseg3wu.v v4, (a0), a1
+       th.vlsseg3wu.v v4, 0(a0), a1
+       th.vlsseg3wu.v v4, (a0), a1, v0.t
+       th.vlsseg3e.v v4, (a0), a1
+       th.vlsseg3e.v v4, 0(a0), a1
+       th.vlsseg3e.v v4, (a0), a1, v0.t
+       th.vssseg3b.v v4, (a0), a1
+       th.vssseg3b.v v4, 0(a0), a1
+       th.vssseg3b.v v4, (a0), a1, v0.t
+       th.vssseg3h.v v4, (a0), a1
+       th.vssseg3h.v v4, 0(a0), a1
+       th.vssseg3h.v v4, (a0), a1, v0.t
+       th.vssseg3w.v v4, (a0), a1
+       th.vssseg3w.v v4, 0(a0), a1
+       th.vssseg3w.v v4, (a0), a1, v0.t
+       th.vssseg3e.v v4, (a0), a1
+       th.vssseg3e.v v4, 0(a0), a1
+       th.vssseg3e.v v4, (a0), a1, v0.t
+
+       th.vlsseg4b.v v4, (a0), a1
+       th.vlsseg4b.v v4, 0(a0), a1
+       th.vlsseg4b.v v4, (a0), a1, v0.t
+       th.vlsseg4h.v v4, (a0), a1
+       th.vlsseg4h.v v4, 0(a0), a1
+       th.vlsseg4h.v v4, (a0), a1, v0.t
+       th.vlsseg4w.v v4, (a0), a1
+       th.vlsseg4w.v v4, 0(a0), a1
+       th.vlsseg4w.v v4, (a0), a1, v0.t
+       th.vlsseg4bu.v v4, (a0), a1
+       th.vlsseg4bu.v v4, 0(a0), a1
+       th.vlsseg4bu.v v4, (a0), a1, v0.t
+       th.vlsseg4hu.v v4, (a0), a1
+       th.vlsseg4hu.v v4, 0(a0), a1
+       th.vlsseg4hu.v v4, (a0), a1, v0.t
+       th.vlsseg4wu.v v4, (a0), a1
+       th.vlsseg4wu.v v4, 0(a0), a1
+       th.vlsseg4wu.v v4, (a0), a1, v0.t
+       th.vlsseg4e.v v4, (a0), a1
+       th.vlsseg4e.v v4, 0(a0), a1
+       th.vlsseg4e.v v4, (a0), a1, v0.t
+       th.vssseg4b.v v4, (a0), a1
+       th.vssseg4b.v v4, 0(a0), a1
+       th.vssseg4b.v v4, (a0), a1, v0.t
+       th.vssseg4h.v v4, (a0), a1
+       th.vssseg4h.v v4, 0(a0), a1
+       th.vssseg4h.v v4, (a0), a1, v0.t
+       th.vssseg4w.v v4, (a0), a1
+       th.vssseg4w.v v4, 0(a0), a1
+       th.vssseg4w.v v4, (a0), a1, v0.t
+       th.vssseg4e.v v4, (a0), a1
+       th.vssseg4e.v v4, 0(a0), a1
+       th.vssseg4e.v v4, (a0), a1, v0.t
+
+       th.vlsseg5b.v v4, (a0), a1
+       th.vlsseg5b.v v4, 0(a0), a1
+       th.vlsseg5b.v v4, (a0), a1, v0.t
+       th.vlsseg5h.v v4, (a0), a1
+       th.vlsseg5h.v v4, 0(a0), a1
+       th.vlsseg5h.v v4, (a0), a1, v0.t
+       th.vlsseg5w.v v4, (a0), a1
+       th.vlsseg5w.v v4, 0(a0), a1
+       th.vlsseg5w.v v4, (a0), a1, v0.t
+       th.vlsseg5bu.v v4, (a0), a1
+       th.vlsseg5bu.v v4, 0(a0), a1
+       th.vlsseg5bu.v v4, (a0), a1, v0.t
+       th.vlsseg5hu.v v4, (a0), a1
+       th.vlsseg5hu.v v4, 0(a0), a1
+       th.vlsseg5hu.v v4, (a0), a1, v0.t
+       th.vlsseg5wu.v v4, (a0), a1
+       th.vlsseg5wu.v v4, 0(a0), a1
+       th.vlsseg5wu.v v4, (a0), a1, v0.t
+       th.vlsseg5e.v v4, (a0), a1
+       th.vlsseg5e.v v4, 0(a0), a1
+       th.vlsseg5e.v v4, (a0), a1, v0.t
+       th.vssseg5b.v v4, (a0), a1
+       th.vssseg5b.v v4, 0(a0), a1
+       th.vssseg5b.v v4, (a0), a1, v0.t
+       th.vssseg5h.v v4, (a0), a1
+       th.vssseg5h.v v4, 0(a0), a1
+       th.vssseg5h.v v4, (a0), a1, v0.t
+       th.vssseg5w.v v4, (a0), a1
+       th.vssseg5w.v v4, 0(a0), a1
+       th.vssseg5w.v v4, (a0), a1, v0.t
+       th.vssseg5e.v v4, (a0), a1
+       th.vssseg5e.v v4, 0(a0), a1
+       th.vssseg5e.v v4, (a0), a1, v0.t
+
+       th.vlsseg6b.v v4, (a0), a1
+       th.vlsseg6b.v v4, 0(a0), a1
+       th.vlsseg6b.v v4, (a0), a1, v0.t
+       th.vlsseg6h.v v4, (a0), a1
+       th.vlsseg6h.v v4, 0(a0), a1
+       th.vlsseg6h.v v4, (a0), a1, v0.t
+       th.vlsseg6w.v v4, (a0), a1
+       th.vlsseg6w.v v4, 0(a0), a1
+       th.vlsseg6w.v v4, (a0), a1, v0.t
+       th.vlsseg6bu.v v4, (a0), a1
+       th.vlsseg6bu.v v4, 0(a0), a1
+       th.vlsseg6bu.v v4, (a0), a1, v0.t
+       th.vlsseg6hu.v v4, (a0), a1
+       th.vlsseg6hu.v v4, 0(a0), a1
+       th.vlsseg6hu.v v4, (a0), a1, v0.t
+       th.vlsseg6wu.v v4, (a0), a1
+       th.vlsseg6wu.v v4, 0(a0), a1
+       th.vlsseg6wu.v v4, (a0), a1, v0.t
+       th.vlsseg6e.v v4, (a0), a1
+       th.vlsseg6e.v v4, 0(a0), a1
+       th.vlsseg6e.v v4, (a0), a1, v0.t
+       th.vssseg6b.v v4, (a0), a1
+       th.vssseg6b.v v4, 0(a0), a1
+       th.vssseg6b.v v4, (a0), a1, v0.t
+       th.vssseg6h.v v4, (a0), a1
+       th.vssseg6h.v v4, 0(a0), a1
+       th.vssseg6h.v v4, (a0), a1, v0.t
+       th.vssseg6w.v v4, (a0), a1
+       th.vssseg6w.v v4, 0(a0), a1
+       th.vssseg6w.v v4, (a0), a1, v0.t
+       th.vssseg6e.v v4, (a0), a1
+       th.vssseg6e.v v4, 0(a0), a1
+       th.vssseg6e.v v4, (a0), a1, v0.t
+
+       th.vlsseg7b.v v4, (a0), a1
+       th.vlsseg7b.v v4, 0(a0), a1
+       th.vlsseg7b.v v4, (a0), a1, v0.t
+       th.vlsseg7h.v v4, (a0), a1
+       th.vlsseg7h.v v4, 0(a0), a1
+       th.vlsseg7h.v v4, (a0), a1, v0.t
+       th.vlsseg7w.v v4, (a0), a1
+       th.vlsseg7w.v v4, 0(a0), a1
+       th.vlsseg7w.v v4, (a0), a1, v0.t
+       th.vlsseg7bu.v v4, (a0), a1
+       th.vlsseg7bu.v v4, 0(a0), a1
+       th.vlsseg7bu.v v4, (a0), a1, v0.t
+       th.vlsseg7hu.v v4, (a0), a1
+       th.vlsseg7hu.v v4, 0(a0), a1
+       th.vlsseg7hu.v v4, (a0), a1, v0.t
+       th.vlsseg7wu.v v4, (a0), a1
+       th.vlsseg7wu.v v4, 0(a0), a1
+       th.vlsseg7wu.v v4, (a0), a1, v0.t
+       th.vlsseg7e.v v4, (a0), a1
+       th.vlsseg7e.v v4, 0(a0), a1
+       th.vlsseg7e.v v4, (a0), a1, v0.t
+       th.vssseg7b.v v4, (a0), a1
+       th.vssseg7b.v v4, 0(a0), a1
+       th.vssseg7b.v v4, (a0), a1, v0.t
+       th.vssseg7h.v v4, (a0), a1
+       th.vssseg7h.v v4, 0(a0), a1
+       th.vssseg7h.v v4, (a0), a1, v0.t
+       th.vssseg7w.v v4, (a0), a1
+       th.vssseg7w.v v4, 0(a0), a1
+       th.vssseg7w.v v4, (a0), a1, v0.t
+       th.vssseg7e.v v4, (a0), a1
+       th.vssseg7e.v v4, 0(a0), a1
+       th.vssseg7e.v v4, (a0), a1, v0.t
+
+       th.vlsseg8b.v v4, (a0), a1
+       th.vlsseg8b.v v4, 0(a0), a1
+       th.vlsseg8b.v v4, (a0), a1, v0.t
+       th.vlsseg8h.v v4, (a0), a1
+       th.vlsseg8h.v v4, 0(a0), a1
+       th.vlsseg8h.v v4, (a0), a1, v0.t
+       th.vlsseg8w.v v4, (a0), a1
+       th.vlsseg8w.v v4, 0(a0), a1
+       th.vlsseg8w.v v4, (a0), a1, v0.t
+       th.vlsseg8bu.v v4, (a0), a1
+       th.vlsseg8bu.v v4, 0(a0), a1
+       th.vlsseg8bu.v v4, (a0), a1, v0.t
+       th.vlsseg8hu.v v4, (a0), a1
+       th.vlsseg8hu.v v4, 0(a0), a1
+       th.vlsseg8hu.v v4, (a0), a1, v0.t
+       th.vlsseg8wu.v v4, (a0), a1
+       th.vlsseg8wu.v v4, 0(a0), a1
+       th.vlsseg8wu.v v4, (a0), a1, v0.t
+       th.vlsseg8e.v v4, (a0), a1
+       th.vlsseg8e.v v4, 0(a0), a1
+       th.vlsseg8e.v v4, (a0), a1, v0.t
+       th.vssseg8b.v v4, (a0), a1
+       th.vssseg8b.v v4, 0(a0), a1
+       th.vssseg8b.v v4, (a0), a1, v0.t
+       th.vssseg8h.v v4, (a0), a1
+       th.vssseg8h.v v4, 0(a0), a1
+       th.vssseg8h.v v4, (a0), a1, v0.t
+       th.vssseg8w.v v4, (a0), a1
+       th.vssseg8w.v v4, 0(a0), a1
+       th.vssseg8w.v v4, (a0), a1, v0.t
+       th.vssseg8e.v v4, (a0), a1
+       th.vssseg8e.v v4, 0(a0), a1
+       th.vssseg8e.v v4, (a0), a1, v0.t
+
+       th.vlxseg2b.v v4, (a0), v12
+       th.vlxseg2b.v v4, 0(a0), v12
+       th.vlxseg2b.v v4, (a0), v12, v0.t
+       th.vlxseg2h.v v4, (a0), v12
+       th.vlxseg2h.v v4, 0(a0), v12
+       th.vlxseg2h.v v4, (a0), v12, v0.t
+       th.vlxseg2w.v v4, (a0), v12
+       th.vlxseg2w.v v4, 0(a0), v12
+       th.vlxseg2w.v v4, (a0), v12, v0.t
+       th.vlxseg2bu.v v4, (a0), v12
+       th.vlxseg2bu.v v4, 0(a0), v12
+       th.vlxseg2bu.v v4, (a0), v12, v0.t
+       th.vlxseg2hu.v v4, (a0), v12
+       th.vlxseg2hu.v v4, 0(a0), v12
+       th.vlxseg2hu.v v4, (a0), v12, v0.t
+       th.vlxseg2wu.v v4, (a0), v12
+       th.vlxseg2wu.v v4, 0(a0), v12
+       th.vlxseg2wu.v v4, (a0), v12, v0.t
+       th.vlxseg2e.v v4, (a0), v12
+       th.vlxseg2e.v v4, 0(a0), v12
+       th.vlxseg2e.v v4, (a0), v12, v0.t
+       th.vsxseg2b.v v4, (a0), v12
+       th.vsxseg2b.v v4, 0(a0), v12
+       th.vsxseg2b.v v4, (a0), v12, v0.t
+       th.vsxseg2h.v v4, (a0), v12
+       th.vsxseg2h.v v4, 0(a0), v12
+       th.vsxseg2h.v v4, (a0), v12, v0.t
+       th.vsxseg2w.v v4, (a0), v12
+       th.vsxseg2w.v v4, 0(a0), v12
+       th.vsxseg2w.v v4, (a0), v12, v0.t
+       th.vsxseg2e.v v4, (a0), v12
+       th.vsxseg2e.v v4, 0(a0), v12
+       th.vsxseg2e.v v4, (a0), v12, v0.t
+
+       th.vlxseg3b.v v4, (a0), v12
+       th.vlxseg3b.v v4, 0(a0), v12
+       th.vlxseg3b.v v4, (a0), v12, v0.t
+       th.vlxseg3h.v v4, (a0), v12
+       th.vlxseg3h.v v4, 0(a0), v12
+       th.vlxseg3h.v v4, (a0), v12, v0.t
+       th.vlxseg3w.v v4, (a0), v12
+       th.vlxseg3w.v v4, 0(a0), v12
+       th.vlxseg3w.v v4, (a0), v12, v0.t
+       th.vlxseg3bu.v v4, (a0), v12
+       th.vlxseg3bu.v v4, 0(a0), v12
+       th.vlxseg3bu.v v4, (a0), v12, v0.t
+       th.vlxseg3hu.v v4, (a0), v12
+       th.vlxseg3hu.v v4, 0(a0), v12
+       th.vlxseg3hu.v v4, (a0), v12, v0.t
+       th.vlxseg3wu.v v4, (a0), v12
+       th.vlxseg3wu.v v4, 0(a0), v12
+       th.vlxseg3wu.v v4, (a0), v12, v0.t
+       th.vlxseg3e.v v4, (a0), v12
+       th.vlxseg3e.v v4, 0(a0), v12
+       th.vlxseg3e.v v4, (a0), v12, v0.t
+       th.vsxseg3b.v v4, (a0), v12
+       th.vsxseg3b.v v4, 0(a0), v12
+       th.vsxseg3b.v v4, (a0), v12, v0.t
+       th.vsxseg3h.v v4, (a0), v12
+       th.vsxseg3h.v v4, 0(a0), v12
+       th.vsxseg3h.v v4, (a0), v12, v0.t
+       th.vsxseg3w.v v4, (a0), v12
+       th.vsxseg3w.v v4, 0(a0), v12
+       th.vsxseg3w.v v4, (a0), v12, v0.t
+       th.vsxseg3e.v v4, (a0), v12
+       th.vsxseg3e.v v4, 0(a0), v12
+       th.vsxseg3e.v v4, (a0), v12, v0.t
+
+       th.vlxseg4b.v v4, (a0), v12
+       th.vlxseg4b.v v4, 0(a0), v12
+       th.vlxseg4b.v v4, (a0), v12, v0.t
+       th.vlxseg4h.v v4, (a0), v12
+       th.vlxseg4h.v v4, 0(a0), v12
+       th.vlxseg4h.v v4, (a0), v12, v0.t
+       th.vlxseg4w.v v4, (a0), v12
+       th.vlxseg4w.v v4, 0(a0), v12
+       th.vlxseg4w.v v4, (a0), v12, v0.t
+       th.vlxseg4bu.v v4, (a0), v12
+       th.vlxseg4bu.v v4, 0(a0), v12
+       th.vlxseg4bu.v v4, (a0), v12, v0.t
+       th.vlxseg4hu.v v4, (a0), v12
+       th.vlxseg4hu.v v4, 0(a0), v12
+       th.vlxseg4hu.v v4, (a0), v12, v0.t
+       th.vlxseg4wu.v v4, (a0), v12
+       th.vlxseg4wu.v v4, 0(a0), v12
+       th.vlxseg4wu.v v4, (a0), v12, v0.t
+       th.vlxseg4e.v v4, (a0), v12
+       th.vlxseg4e.v v4, 0(a0), v12
+       th.vlxseg4e.v v4, (a0), v12, v0.t
+       th.vsxseg4b.v v4, (a0), v12
+       th.vsxseg4b.v v4, 0(a0), v12
+       th.vsxseg4b.v v4, (a0), v12, v0.t
+       th.vsxseg4h.v v4, (a0), v12
+       th.vsxseg4h.v v4, 0(a0), v12
+       th.vsxseg4h.v v4, (a0), v12, v0.t
+       th.vsxseg4w.v v4, (a0), v12
+       th.vsxseg4w.v v4, 0(a0), v12
+       th.vsxseg4w.v v4, (a0), v12, v0.t
+       th.vsxseg4e.v v4, (a0), v12
+       th.vsxseg4e.v v4, 0(a0), v12
+       th.vsxseg4e.v v4, (a0), v12, v0.t
+
+       th.vlxseg5b.v v4, (a0), v12
+       th.vlxseg5b.v v4, 0(a0), v12
+       th.vlxseg5b.v v4, (a0), v12, v0.t
+       th.vlxseg5h.v v4, (a0), v12
+       th.vlxseg5h.v v4, 0(a0), v12
+       th.vlxseg5h.v v4, (a0), v12, v0.t
+       th.vlxseg5w.v v4, (a0), v12
+       th.vlxseg5w.v v4, 0(a0), v12
+       th.vlxseg5w.v v4, (a0), v12, v0.t
+       th.vlxseg5bu.v v4, (a0), v12
+       th.vlxseg5bu.v v4, 0(a0), v12
+       th.vlxseg5bu.v v4, (a0), v12, v0.t
+       th.vlxseg5hu.v v4, (a0), v12
+       th.vlxseg5hu.v v4, 0(a0), v12
+       th.vlxseg5hu.v v4, (a0), v12, v0.t
+       th.vlxseg5wu.v v4, (a0), v12
+       th.vlxseg5wu.v v4, 0(a0), v12
+       th.vlxseg5wu.v v4, (a0), v12, v0.t
+       th.vlxseg5e.v v4, (a0), v12
+       th.vlxseg5e.v v4, 0(a0), v12
+       th.vlxseg5e.v v4, (a0), v12, v0.t
+       th.vsxseg5b.v v4, (a0), v12
+       th.vsxseg5b.v v4, 0(a0), v12
+       th.vsxseg5b.v v4, (a0), v12, v0.t
+       th.vsxseg5h.v v4, (a0), v12
+       th.vsxseg5h.v v4, 0(a0), v12
+       th.vsxseg5h.v v4, (a0), v12, v0.t
+       th.vsxseg5w.v v4, (a0), v12
+       th.vsxseg5w.v v4, 0(a0), v12
+       th.vsxseg5w.v v4, (a0), v12, v0.t
+       th.vsxseg5e.v v4, (a0), v12
+       th.vsxseg5e.v v4, 0(a0), v12
+       th.vsxseg5e.v v4, (a0), v12, v0.t
+
+       th.vlxseg6b.v v4, (a0), v12
+       th.vlxseg6b.v v4, 0(a0), v12
+       th.vlxseg6b.v v4, (a0), v12, v0.t
+       th.vlxseg6h.v v4, (a0), v12
+       th.vlxseg6h.v v4, 0(a0), v12
+       th.vlxseg6h.v v4, (a0), v12, v0.t
+       th.vlxseg6w.v v4, (a0), v12
+       th.vlxseg6w.v v4, 0(a0), v12
+       th.vlxseg6w.v v4, (a0), v12, v0.t
+       th.vlxseg6bu.v v4, (a0), v12
+       th.vlxseg6bu.v v4, 0(a0), v12
+       th.vlxseg6bu.v v4, (a0), v12, v0.t
+       th.vlxseg6hu.v v4, (a0), v12
+       th.vlxseg6hu.v v4, 0(a0), v12
+       th.vlxseg6hu.v v4, (a0), v12, v0.t
+       th.vlxseg6wu.v v4, (a0), v12
+       th.vlxseg6wu.v v4, 0(a0), v12
+       th.vlxseg6wu.v v4, (a0), v12, v0.t
+       th.vlxseg6e.v v4, (a0), v12
+       th.vlxseg6e.v v4, 0(a0), v12
+       th.vlxseg6e.v v4, (a0), v12, v0.t
+       th.vsxseg6b.v v4, (a0), v12
+       th.vsxseg6b.v v4, 0(a0), v12
+       th.vsxseg6b.v v4, (a0), v12, v0.t
+       th.vsxseg6h.v v4, (a0), v12
+       th.vsxseg6h.v v4, 0(a0), v12
+       th.vsxseg6h.v v4, (a0), v12, v0.t
+       th.vsxseg6w.v v4, (a0), v12
+       th.vsxseg6w.v v4, 0(a0), v12
+       th.vsxseg6w.v v4, (a0), v12, v0.t
+       th.vsxseg6e.v v4, (a0), v12
+       th.vsxseg6e.v v4, 0(a0), v12
+       th.vsxseg6e.v v4, (a0), v12, v0.t
+
+       th.vlxseg7b.v v4, (a0), v12
+       th.vlxseg7b.v v4, 0(a0), v12
+       th.vlxseg7b.v v4, (a0), v12, v0.t
+       th.vlxseg7h.v v4, (a0), v12
+       th.vlxseg7h.v v4, 0(a0), v12
+       th.vlxseg7h.v v4, (a0), v12, v0.t
+       th.vlxseg7w.v v4, (a0), v12
+       th.vlxseg7w.v v4, 0(a0), v12
+       th.vlxseg7w.v v4, (a0), v12, v0.t
+       th.vlxseg7bu.v v4, (a0), v12
+       th.vlxseg7bu.v v4, 0(a0), v12
+       th.vlxseg7bu.v v4, (a0), v12, v0.t
+       th.vlxseg7hu.v v4, (a0), v12
+       th.vlxseg7hu.v v4, 0(a0), v12
+       th.vlxseg7hu.v v4, (a0), v12, v0.t
+       th.vlxseg7wu.v v4, (a0), v12
+       th.vlxseg7wu.v v4, 0(a0), v12
+       th.vlxseg7wu.v v4, (a0), v12, v0.t
+       th.vlxseg7e.v v4, (a0), v12
+       th.vlxseg7e.v v4, 0(a0), v12
+       th.vlxseg7e.v v4, (a0), v12, v0.t
+       th.vsxseg7b.v v4, (a0), v12
+       th.vsxseg7b.v v4, 0(a0), v12
+       th.vsxseg7b.v v4, (a0), v12, v0.t
+       th.vsxseg7h.v v4, (a0), v12
+       th.vsxseg7h.v v4, 0(a0), v12
+       th.vsxseg7h.v v4, (a0), v12, v0.t
+       th.vsxseg7w.v v4, (a0), v12
+       th.vsxseg7w.v v4, 0(a0), v12
+       th.vsxseg7w.v v4, (a0), v12, v0.t
+       th.vsxseg7e.v v4, (a0), v12
+       th.vsxseg7e.v v4, 0(a0), v12
+       th.vsxseg7e.v v4, (a0), v12, v0.t
+
+       th.vlxseg8b.v v4, (a0), v12
+       th.vlxseg8b.v v4, 0(a0), v12
+       th.vlxseg8b.v v4, (a0), v12, v0.t
+       th.vlxseg8h.v v4, (a0), v12
+       th.vlxseg8h.v v4, 0(a0), v12
+       th.vlxseg8h.v v4, (a0), v12, v0.t
+       th.vlxseg8w.v v4, (a0), v12
+       th.vlxseg8w.v v4, 0(a0), v12
+       th.vlxseg8w.v v4, (a0), v12, v0.t
+       th.vlxseg8bu.v v4, (a0), v12
+       th.vlxseg8bu.v v4, 0(a0), v12
+       th.vlxseg8bu.v v4, (a0), v12, v0.t
+       th.vlxseg8hu.v v4, (a0), v12
+       th.vlxseg8hu.v v4, 0(a0), v12
+       th.vlxseg8hu.v v4, (a0), v12, v0.t
+       th.vlxseg8wu.v v4, (a0), v12
+       th.vlxseg8wu.v v4, 0(a0), v12
+       th.vlxseg8wu.v v4, (a0), v12, v0.t
+       th.vlxseg8e.v v4, (a0), v12
+       th.vlxseg8e.v v4, 0(a0), v12
+       th.vlxseg8e.v v4, (a0), v12, v0.t
+       th.vsxseg8b.v v4, (a0), v12
+       th.vsxseg8b.v v4, 0(a0), v12
+       th.vsxseg8b.v v4, (a0), v12, v0.t
+       th.vsxseg8h.v v4, (a0), v12
+       th.vsxseg8h.v v4, 0(a0), v12
+       th.vsxseg8h.v v4, (a0), v12, v0.t
+       th.vsxseg8w.v v4, (a0), v12
+       th.vsxseg8w.v v4, 0(a0), v12
+       th.vsxseg8w.v v4, (a0), v12, v0.t
+       th.vsxseg8e.v v4, (a0), v12
+       th.vsxseg8e.v v4, 0(a0), v12
+       th.vsxseg8e.v v4, (a0), v12, v0.t
+
+       th.vlseg2bff.v v4, (a0)
+       th.vlseg2bff.v v4, 0(a0)
+       th.vlseg2bff.v v4, (a0), v0.t
+       th.vlseg2hff.v v4, (a0)
+       th.vlseg2hff.v v4, 0(a0)
+       th.vlseg2hff.v v4, (a0), v0.t
+       th.vlseg2wff.v v4, (a0)
+       th.vlseg2wff.v v4, 0(a0)
+       th.vlseg2wff.v v4, (a0), v0.t
+       th.vlseg2buff.v v4, (a0)
+       th.vlseg2buff.v v4, 0(a0)
+       th.vlseg2buff.v v4, (a0), v0.t
+       th.vlseg2huff.v v4, (a0)
+       th.vlseg2huff.v v4, 0(a0)
+       th.vlseg2huff.v v4, (a0), v0.t
+       th.vlseg2wuff.v v4, (a0)
+       th.vlseg2wuff.v v4, 0(a0)
+       th.vlseg2wuff.v v4, (a0), v0.t
+       th.vlseg2eff.v v4, (a0)
+       th.vlseg2eff.v v4, 0(a0)
+       th.vlseg2eff.v v4, (a0), v0.t
+
+       th.vlseg3bff.v v4, (a0)
+       th.vlseg3bff.v v4, 0(a0)
+       th.vlseg3bff.v v4, (a0), v0.t
+       th.vlseg3hff.v v4, (a0)
+       th.vlseg3hff.v v4, 0(a0)
+       th.vlseg3hff.v v4, (a0), v0.t
+       th.vlseg3wff.v v4, (a0)
+       th.vlseg3wff.v v4, 0(a0)
+       th.vlseg3wff.v v4, (a0), v0.t
+       th.vlseg3buff.v v4, (a0)
+       th.vlseg3buff.v v4, 0(a0)
+       th.vlseg3buff.v v4, (a0), v0.t
+       th.vlseg3huff.v v4, (a0)
+       th.vlseg3huff.v v4, 0(a0)
+       th.vlseg3huff.v v4, (a0), v0.t
+       th.vlseg3wuff.v v4, (a0)
+       th.vlseg3wuff.v v4, 0(a0)
+       th.vlseg3wuff.v v4, (a0), v0.t
+       th.vlseg3eff.v v4, (a0)
+       th.vlseg3eff.v v4, 0(a0)
+       th.vlseg3eff.v v4, (a0), v0.t
+
+       th.vlseg4bff.v v4, (a0)
+       th.vlseg4bff.v v4, 0(a0)
+       th.vlseg4bff.v v4, (a0), v0.t
+       th.vlseg4hff.v v4, (a0)
+       th.vlseg4hff.v v4, 0(a0)
+       th.vlseg4hff.v v4, (a0), v0.t
+       th.vlseg4wff.v v4, (a0)
+       th.vlseg4wff.v v4, 0(a0)
+       th.vlseg4wff.v v4, (a0), v0.t
+       th.vlseg4buff.v v4, (a0)
+       th.vlseg4buff.v v4, 0(a0)
+       th.vlseg4buff.v v4, (a0), v0.t
+       th.vlseg4huff.v v4, (a0)
+       th.vlseg4huff.v v4, 0(a0)
+       th.vlseg4huff.v v4, (a0), v0.t
+       th.vlseg4wuff.v v4, (a0)
+       th.vlseg4wuff.v v4, 0(a0)
+       th.vlseg4wuff.v v4, (a0), v0.t
+       th.vlseg4eff.v v4, (a0)
+       th.vlseg4eff.v v4, 0(a0)
+       th.vlseg4eff.v v4, (a0), v0.t
+
+       th.vlseg5bff.v v4, (a0)
+       th.vlseg5bff.v v4, 0(a0)
+       th.vlseg5bff.v v4, (a0), v0.t
+       th.vlseg5hff.v v4, (a0)
+       th.vlseg5hff.v v4, 0(a0)
+       th.vlseg5hff.v v4, (a0), v0.t
+       th.vlseg5wff.v v4, (a0)
+       th.vlseg5wff.v v4, 0(a0)
+       th.vlseg5wff.v v4, (a0), v0.t
+       th.vlseg5buff.v v4, (a0)
+       th.vlseg5buff.v v4, 0(a0)
+       th.vlseg5buff.v v4, (a0), v0.t
+       th.vlseg5huff.v v4, (a0)
+       th.vlseg5huff.v v4, 0(a0)
+       th.vlseg5huff.v v4, (a0), v0.t
+       th.vlseg5wuff.v v4, (a0)
+       th.vlseg5wuff.v v4, 0(a0)
+       th.vlseg5wuff.v v4, (a0), v0.t
+       th.vlseg5eff.v v4, (a0)
+       th.vlseg5eff.v v4, 0(a0)
+       th.vlseg5eff.v v4, (a0), v0.t
+
+       th.vlseg6bff.v v4, (a0)
+       th.vlseg6bff.v v4, 0(a0)
+       th.vlseg6bff.v v4, (a0), v0.t
+       th.vlseg6hff.v v4, (a0)
+       th.vlseg6hff.v v4, 0(a0)
+       th.vlseg6hff.v v4, (a0), v0.t
+       th.vlseg6wff.v v4, (a0)
+       th.vlseg6wff.v v4, 0(a0)
+       th.vlseg6wff.v v4, (a0), v0.t
+       th.vlseg6buff.v v4, (a0)
+       th.vlseg6buff.v v4, 0(a0)
+       th.vlseg6buff.v v4, (a0), v0.t
+       th.vlseg6huff.v v4, (a0)
+       th.vlseg6huff.v v4, 0(a0)
+       th.vlseg6huff.v v4, (a0), v0.t
+       th.vlseg6wuff.v v4, (a0)
+       th.vlseg6wuff.v v4, 0(a0)
+       th.vlseg6wuff.v v4, (a0), v0.t
+       th.vlseg6eff.v v4, (a0)
+       th.vlseg6eff.v v4, 0(a0)
+       th.vlseg6eff.v v4, (a0), v0.t
+
+       th.vlseg7bff.v v4, (a0)
+       th.vlseg7bff.v v4, 0(a0)
+       th.vlseg7bff.v v4, (a0), v0.t
+       th.vlseg7hff.v v4, (a0)
+       th.vlseg7hff.v v4, 0(a0)
+       th.vlseg7hff.v v4, (a0), v0.t
+       th.vlseg7wff.v v4, (a0)
+       th.vlseg7wff.v v4, 0(a0)
+       th.vlseg7wff.v v4, (a0), v0.t
+       th.vlseg7buff.v v4, (a0)
+       th.vlseg7buff.v v4, 0(a0)
+       th.vlseg7buff.v v4, (a0), v0.t
+       th.vlseg7huff.v v4, (a0)
+       th.vlseg7huff.v v4, 0(a0)
+       th.vlseg7huff.v v4, (a0), v0.t
+       th.vlseg7wuff.v v4, (a0)
+       th.vlseg7wuff.v v4, 0(a0)
+       th.vlseg7wuff.v v4, (a0), v0.t
+       th.vlseg7eff.v v4, (a0)
+       th.vlseg7eff.v v4, 0(a0)
+       th.vlseg7eff.v v4, (a0), v0.t
+
+       th.vlseg8bff.v v4, (a0)
+       th.vlseg8bff.v v4, 0(a0)
+       th.vlseg8bff.v v4, (a0), v0.t
+       th.vlseg8hff.v v4, (a0)
+       th.vlseg8hff.v v4, 0(a0)
+       th.vlseg8hff.v v4, (a0), v0.t
+       th.vlseg8wff.v v4, (a0)
+       th.vlseg8wff.v v4, 0(a0)
+       th.vlseg8wff.v v4, (a0), v0.t
+       th.vlseg8buff.v v4, (a0)
+       th.vlseg8buff.v v4, 0(a0)
+       th.vlseg8buff.v v4, (a0), v0.t
+       th.vlseg8huff.v v4, (a0)
+       th.vlseg8huff.v v4, 0(a0)
+       th.vlseg8huff.v v4, (a0), v0.t
+       th.vlseg8wuff.v v4, (a0)
+       th.vlseg8wuff.v v4, 0(a0)
+       th.vlseg8wuff.v v4, (a0), v0.t
+       th.vlseg8eff.v v4, (a0)
+       th.vlseg8eff.v v4, 0(a0)
+       th.vlseg8eff.v v4, (a0), v0.t

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 792958b892515d181b78631994b45017080fd28c..6556de2b17dbc6b48bdf45a48430963b4faa603c 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2681,6 +2681,175 @@
 #define MASK_TH_VLHFFV   0xfdf0707f
 #define MATCH_TH_VLWFFV  0x11006007
 #define MASK_TH_VLWFFV   0xfdf0707f
+#define MATCH_TH_VLSEG2BV 0x30000007
+#define MASK_TH_VLSEG2BV 0xfdf0707f
+#define MATCH_TH_VLSEG2HV 0x30005007
+#define MASK_TH_VLSEG2HV 0xfdf0707f
+#define MATCH_TH_VLSEG2WV 0x30006007
+#define MASK_TH_VLSEG2WV 0xfdf0707f
+#define MATCH_TH_VLSEG3BV 0x50000007
+#define MASK_TH_VLSEG3BV 0xfdf0707f
+#define MATCH_TH_VLSEG3HV 0x50005007
+#define MASK_TH_VLSEG3HV 0xfdf0707f
+#define MATCH_TH_VLSEG3WV 0x50006007
+#define MASK_TH_VLSEG3WV 0xfdf0707f
+#define MATCH_TH_VLSEG4BV 0x70000007
+#define MASK_TH_VLSEG4BV 0xfdf0707f
+#define MATCH_TH_VLSEG4HV 0x70005007
+#define MASK_TH_VLSEG4HV 0xfdf0707f
+#define MATCH_TH_VLSEG4WV 0x70006007
+#define MASK_TH_VLSEG4WV 0xfdf0707f
+#define MATCH_TH_VLSEG5BV 0x90000007
+#define MASK_TH_VLSEG5BV 0xfdf0707f
+#define MATCH_TH_VLSEG5HV 0x90005007
+#define MASK_TH_VLSEG5HV 0xfdf0707f
+#define MATCH_TH_VLSEG5WV 0x90006007
+#define MASK_TH_VLSEG5WV 0xfdf0707f
+#define MATCH_TH_VLSEG6BV 0xb0000007
+#define MASK_TH_VLSEG6BV 0xfdf0707f
+#define MATCH_TH_VLSEG6HV 0xb0005007
+#define MASK_TH_VLSEG6HV 0xfdf0707f
+#define MATCH_TH_VLSEG6WV 0xb0006007
+#define MASK_TH_VLSEG6WV 0xfdf0707f
+#define MATCH_TH_VLSEG7BV 0xd0000007
+#define MASK_TH_VLSEG7BV 0xfdf0707f
+#define MATCH_TH_VLSEG7HV 0xd0005007
+#define MASK_TH_VLSEG7HV 0xfdf0707f
+#define MATCH_TH_VLSEG7WV 0xd0006007
+#define MASK_TH_VLSEG7WV 0xfdf0707f
+#define MATCH_TH_VLSEG8BV 0xf0000007
+#define MASK_TH_VLSEG8BV 0xfdf0707f
+#define MATCH_TH_VLSEG8HV 0xf0005007
+#define MASK_TH_VLSEG8HV 0xfdf0707f
+#define MATCH_TH_VLSEG8WV 0xf0006007
+#define MASK_TH_VLSEG8WV 0xfdf0707f
+#define MATCH_TH_VLSSEG2BV 0x38000007
+#define MASK_TH_VLSSEG2BV 0xfc00707f
+#define MATCH_TH_VLSSEG2HV 0x38005007
+#define MASK_TH_VLSSEG2HV 0xfc00707f
+#define MATCH_TH_VLSSEG2WV 0x38006007
+#define MASK_TH_VLSSEG2WV 0xfc00707f
+#define MATCH_TH_VLSSEG3BV 0x58000007
+#define MASK_TH_VLSSEG3BV 0xfc00707f
+#define MATCH_TH_VLSSEG3HV 0x58005007
+#define MASK_TH_VLSSEG3HV 0xfc00707f
+#define MATCH_TH_VLSSEG3WV 0x58006007
+#define MASK_TH_VLSSEG3WV 0xfc00707f
+#define MATCH_TH_VLSSEG4BV 0x78000007
+#define MASK_TH_VLSSEG4BV 0xfc00707f
+#define MATCH_TH_VLSSEG4HV 0x78005007
+#define MASK_TH_VLSSEG4HV 0xfc00707f
+#define MATCH_TH_VLSSEG4WV 0x78006007
+#define MASK_TH_VLSSEG4WV 0xfc00707f
+#define MATCH_TH_VLSSEG5BV 0x98000007
+#define MASK_TH_VLSSEG5BV 0xfc00707f
+#define MATCH_TH_VLSSEG5HV 0x98005007
+#define MASK_TH_VLSSEG5HV 0xfc00707f
+#define MATCH_TH_VLSSEG5WV 0x98006007
+#define MASK_TH_VLSSEG5WV 0xfc00707f
+#define MATCH_TH_VLSSEG6BV 0xb8000007
+#define MASK_TH_VLSSEG6BV 0xfc00707f
+#define MATCH_TH_VLSSEG6HV 0xb8005007
+#define MASK_TH_VLSSEG6HV 0xfc00707f
+#define MATCH_TH_VLSSEG6WV 0xb8006007
+#define MASK_TH_VLSSEG6WV 0xfc00707f
+#define MATCH_TH_VLSSEG7BV 0xd8000007
+#define MASK_TH_VLSSEG7BV 0xfc00707f
+#define MATCH_TH_VLSSEG7HV 0xd8005007
+#define MASK_TH_VLSSEG7HV 0xfc00707f
+#define MATCH_TH_VLSSEG7WV 0xd8006007
+#define MASK_TH_VLSSEG7WV 0xfc00707f
+#define MATCH_TH_VLSSEG8BV 0xf8000007
+#define MASK_TH_VLSSEG8BV 0xfc00707f
+#define MATCH_TH_VLSSEG8HV 0xf8005007
+#define MASK_TH_VLSSEG8HV 0xfc00707f
+#define MATCH_TH_VLSSEG8WV 0xf8006007
+#define MASK_TH_VLSSEG8WV 0xfc00707f
+#define MATCH_TH_VLXSEG2BV 0x3c000007
+#define MASK_TH_VLXSEG2BV 0xfc00707f
+#define MATCH_TH_VLXSEG2HV 0x3c005007
+#define MASK_TH_VLXSEG2HV 0xfc00707f
+#define MATCH_TH_VLXSEG2WV 0x3c006007
+#define MASK_TH_VLXSEG2WV 0xfc00707f
+#define MATCH_TH_VLXSEG3BV 0x5c000007
+#define MASK_TH_VLXSEG3BV 0xfc00707f
+#define MATCH_TH_VLXSEG3HV 0x5c005007
+#define MASK_TH_VLXSEG3HV 0xfc00707f
+#define MATCH_TH_VLXSEG3WV 0x5c006007
+#define MASK_TH_VLXSEG3WV 0xfc00707f
+#define MATCH_TH_VLXSEG4BV 0x7c000007
+#define MASK_TH_VLXSEG4BV 0xfc00707f
+#define MATCH_TH_VLXSEG4HV 0x7c005007
+#define MASK_TH_VLXSEG4HV 0xfc00707f
+#define MATCH_TH_VLXSEG4WV 0x7c006007
+#define MASK_TH_VLXSEG4WV 0xfc00707f
+#define MATCH_TH_VLXSEG5BV 0x9c000007
+#define MASK_TH_VLXSEG5BV 0xfc00707f
+#define MATCH_TH_VLXSEG5HV 0x9c005007
+#define MASK_TH_VLXSEG5HV 0xfc00707f
+#define MATCH_TH_VLXSEG5WV 0x9c006007
+#define MASK_TH_VLXSEG5WV 0xfc00707f
+#define MATCH_TH_VLXSEG6BV 0xbc000007
+#define MASK_TH_VLXSEG6BV 0xfc00707f
+#define MATCH_TH_VLXSEG6HV 0xbc005007
+#define MASK_TH_VLXSEG6HV 0xfc00707f
+#define MATCH_TH_VLXSEG6WV 0xbc006007
+#define MASK_TH_VLXSEG6WV 0xfc00707f
+#define MATCH_TH_VLXSEG7BV 0xdc000007
+#define MASK_TH_VLXSEG7BV 0xfc00707f
+#define MATCH_TH_VLXSEG7HV 0xdc005007
+#define MASK_TH_VLXSEG7HV 0xfc00707f
+#define MATCH_TH_VLXSEG7WV 0xdc006007
+#define MASK_TH_VLXSEG7WV 0xfc00707f
+#define MATCH_TH_VLXSEG8BV 0xfc000007
+#define MASK_TH_VLXSEG8BV 0xfc00707f
+#define MATCH_TH_VLXSEG8HV 0xfc005007
+#define MASK_TH_VLXSEG8HV 0xfc00707f
+#define MATCH_TH_VLXSEG8WV 0xfc006007
+#define MASK_TH_VLXSEG8WV 0xfc00707f
+#define MATCH_TH_VLSEG2BFFV 0x31000007
+#define MASK_TH_VLSEG2BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2HFFV 0x31005007
+#define MASK_TH_VLSEG2HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2WFFV 0x31006007
+#define MASK_TH_VLSEG2WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3BFFV 0x51000007
+#define MASK_TH_VLSEG3BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3HFFV 0x51005007
+#define MASK_TH_VLSEG3HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3WFFV 0x51006007
+#define MASK_TH_VLSEG3WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4BFFV 0x71000007
+#define MASK_TH_VLSEG4BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4HFFV 0x71005007
+#define MASK_TH_VLSEG4HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4WFFV 0x71006007
+#define MASK_TH_VLSEG4WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5BFFV 0x91000007
+#define MASK_TH_VLSEG5BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5HFFV 0x91005007
+#define MASK_TH_VLSEG5HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5WFFV 0x91006007
+#define MASK_TH_VLSEG5WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6BFFV 0xb1000007
+#define MASK_TH_VLSEG6BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6HFFV 0xb1005007
+#define MASK_TH_VLSEG6HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6WFFV 0xb1006007
+#define MASK_TH_VLSEG6WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7BFFV 0xd1000007
+#define MASK_TH_VLSEG7BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7HFFV 0xd1005007
+#define MASK_TH_VLSEG7HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7WFFV 0xd1006007
+#define MASK_TH_VLSEG7WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8BFFV 0xf1000007
+#define MASK_TH_VLSEG8BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8HFFV 0xf1005007
+#define MASK_TH_VLSEG8HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8WFFV 0xf1006007
+#define MASK_TH_VLSEG8WFFV 0xfdf0707f
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 54c1e8a62d96dcdc986c3a0bffd504b7c22d1dec..71e4453cd4355d543091e9ef7cdf69060905f8da 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2281,6 +2281,286 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vlhuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF },
 {"th.vlwuff.v",   0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF },
 {"th.vleff.v",    0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF },
+{"th.vlseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2BV, MASK_TH_VLSEG2BV, match_opcode, INSN_DREF },
+{"th.vlseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2HV, MASK_TH_VLSEG2HV, match_opcode, INSN_DREF },
+{"th.vlseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2WV, MASK_TH_VLSEG2WV, match_opcode, INSN_DREF },
+{"th.vlseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF },
+{"th.vlseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E16V, MASK_VLSEG2E16V, match_opcode, INSN_DREF },
+{"th.vlseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E32V, MASK_VLSEG2E32V, match_opcode, INSN_DREF },
+{"th.vlseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF },
+{"th.vsseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vsseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E16V, MASK_VSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vsseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E32V, MASK_VSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vsseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vlseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3BV, MASK_TH_VLSEG3BV, match_opcode, INSN_DREF },
+{"th.vlseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3HV, MASK_TH_VLSEG3HV, match_opcode, INSN_DREF },
+{"th.vlseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3WV, MASK_TH_VLSEG3WV, match_opcode, INSN_DREF },
+{"th.vlseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E8V, MASK_VLSEG3E8V, match_opcode, INSN_DREF },
+{"th.vlseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E16V, MASK_VLSEG3E16V, match_opcode, INSN_DREF },
+{"th.vlseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E32V, MASK_VLSEG3E32V, match_opcode, INSN_DREF },
+{"th.vlseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF },
+{"th.vsseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E8V, MASK_VSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vsseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E16V, MASK_VSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vsseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E32V, MASK_VSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vsseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vlseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4BV, MASK_TH_VLSEG4BV, match_opcode, INSN_DREF },
+{"th.vlseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4HV, MASK_TH_VLSEG4HV, match_opcode, INSN_DREF },
+{"th.vlseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4WV, MASK_TH_VLSEG4WV, match_opcode, INSN_DREF },
+{"th.vlseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E8V, MASK_VLSEG4E8V, match_opcode, INSN_DREF },
+{"th.vlseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E16V, MASK_VLSEG4E16V, match_opcode, INSN_DREF },
+{"th.vlseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E32V, MASK_VLSEG4E32V, match_opcode, INSN_DREF },
+{"th.vlseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF },
+{"th.vsseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E8V, MASK_VSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vsseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E16V, MASK_VSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vsseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E32V, MASK_VSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vsseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vlseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5BV, MASK_TH_VLSEG5BV, match_opcode, INSN_DREF },
+{"th.vlseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5HV, MASK_TH_VLSEG5HV, match_opcode, INSN_DREF },
+{"th.vlseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5WV, MASK_TH_VLSEG5WV, match_opcode, INSN_DREF },
+{"th.vlseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E8V, MASK_VLSEG5E8V, match_opcode, INSN_DREF },
+{"th.vlseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E16V, MASK_VLSEG5E16V, match_opcode, INSN_DREF },
+{"th.vlseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E32V, MASK_VLSEG5E32V, match_opcode, INSN_DREF },
+{"th.vlseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF },
+{"th.vsseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E8V, MASK_VSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vsseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E16V, MASK_VSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vsseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E32V, MASK_VSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vsseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vlseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6BV, MASK_TH_VLSEG6BV, match_opcode, INSN_DREF },
+{"th.vlseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6HV, MASK_TH_VLSEG6HV, match_opcode, INSN_DREF },
+{"th.vlseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6WV, MASK_TH_VLSEG6WV, match_opcode, INSN_DREF },
+{"th.vlseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E8V, MASK_VLSEG6E8V, match_opcode, INSN_DREF },
+{"th.vlseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E16V, MASK_VLSEG6E16V, match_opcode, INSN_DREF },
+{"th.vlseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E32V, MASK_VLSEG6E32V, match_opcode, INSN_DREF },
+{"th.vlseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF },
+{"th.vsseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E8V, MASK_VSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vsseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E16V, MASK_VSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vsseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E32V, MASK_VSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vsseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vlseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7BV, MASK_TH_VLSEG7BV, match_opcode, INSN_DREF },
+{"th.vlseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7HV, MASK_TH_VLSEG7HV, match_opcode, INSN_DREF },
+{"th.vlseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7WV, MASK_TH_VLSEG7WV, match_opcode, INSN_DREF },
+{"th.vlseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E8V, MASK_VLSEG7E8V, match_opcode, INSN_DREF },
+{"th.vlseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E16V, MASK_VLSEG7E16V, match_opcode, INSN_DREF },
+{"th.vlseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E32V, MASK_VLSEG7E32V, match_opcode, INSN_DREF },
+{"th.vlseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF },
+{"th.vsseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E8V, MASK_VSSEG7E8V, match_opcode, INSN_DREF },
+{"th.vsseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E16V, MASK_VSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vsseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E32V, MASK_VSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vsseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vlseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8BV, MASK_TH_VLSEG8BV, match_opcode, INSN_DREF },
+{"th.vlseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8HV, MASK_TH_VLSEG8HV, match_opcode, INSN_DREF },
+{"th.vlseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8WV, MASK_TH_VLSEG8WV, match_opcode, INSN_DREF },
+{"th.vlseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E8V, MASK_VLSEG8E8V, match_opcode, INSN_DREF },
+{"th.vlseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E16V, MASK_VLSEG8E16V, match_opcode, INSN_DREF },
+{"th.vlseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF },
+{"th.vlseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF },
+{"th.vsseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E8V, MASK_VSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vsseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E16V, MASK_VSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vsseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vsseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vlsseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2BV, MASK_TH_VLSSEG2BV, match_opcode, INSN_DREF },
+{"th.vlsseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2HV, MASK_TH_VLSSEG2HV, match_opcode, INSN_DREF },
+{"th.vlsseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG2WV, MASK_TH_VLSSEG2WV, match_opcode, INSN_DREF },
+{"th.vlsseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vlsseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E16V, MASK_VLSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vlsseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E32V, MASK_VLSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vlsseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vssseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF },
+{"th.vssseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E16V, MASK_VSSSEG2E16V, match_opcode, INSN_DREF },
+{"th.vssseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E32V, MASK_VSSSEG2E32V, match_opcode, INSN_DREF },
+{"th.vssseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF },
+{"th.vlsseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3BV, MASK_TH_VLSSEG3BV, match_opcode, INSN_DREF },
+{"th.vlsseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3HV, MASK_TH_VLSSEG3HV, match_opcode, INSN_DREF },
+{"th.vlsseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG3WV, MASK_TH_VLSSEG3WV, match_opcode, INSN_DREF },
+{"th.vlsseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E8V, MASK_VLSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vlsseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E16V, MASK_VLSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vlsseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E32V, MASK_VLSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vlsseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vssseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E8V, MASK_VSSSEG3E8V, match_opcode, INSN_DREF },
+{"th.vssseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E16V, MASK_VSSSEG3E16V, match_opcode, INSN_DREF },
+{"th.vssseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E32V, MASK_VSSSEG3E32V, match_opcode, INSN_DREF },
+{"th.vssseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF },
+{"th.vlsseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4BV, MASK_TH_VLSSEG4BV, match_opcode, INSN_DREF },
+{"th.vlsseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4HV, MASK_TH_VLSSEG4HV, match_opcode, INSN_DREF },
+{"th.vlsseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG4WV, MASK_TH_VLSSEG4WV, match_opcode, INSN_DREF },
+{"th.vlsseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E8V, MASK_VLSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vlsseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E16V, MASK_VLSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vlsseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E32V, MASK_VLSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vlsseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vssseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E8V, MASK_VSSSEG4E8V, match_opcode, INSN_DREF },
+{"th.vssseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E16V, MASK_VSSSEG4E16V, match_opcode, INSN_DREF },
+{"th.vssseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E32V, MASK_VSSSEG4E32V, match_opcode, INSN_DREF },
+{"th.vssseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF },
+{"th.vlsseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5BV, MASK_TH_VLSSEG5BV, match_opcode, INSN_DREF },
+{"th.vlsseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5HV, MASK_TH_VLSSEG5HV, match_opcode, INSN_DREF },
+{"th.vlsseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG5WV, MASK_TH_VLSSEG5WV, match_opcode, INSN_DREF },
+{"th.vlsseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E8V, MASK_VLSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vlsseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E16V, MASK_VLSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vlsseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E32V, MASK_VLSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vlsseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vssseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E8V, MASK_VSSSEG5E8V, match_opcode, INSN_DREF },
+{"th.vssseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E16V, MASK_VSSSEG5E16V, match_opcode, INSN_DREF },
+{"th.vssseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E32V, MASK_VSSSEG5E32V, match_opcode, INSN_DREF },
+{"th.vssseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF },
+{"th.vlsseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6BV, MASK_TH_VLSSEG6BV, match_opcode, INSN_DREF },
+{"th.vlsseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6HV, MASK_TH_VLSSEG6HV, match_opcode, INSN_DREF },
+{"th.vlsseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG6WV, MASK_TH_VLSSEG6WV, match_opcode, INSN_DREF },
+{"th.vlsseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E8V, MASK_VLSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vlsseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E16V, MASK_VLSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vlsseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E32V, MASK_VLSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vlsseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vssseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E8V, MASK_VSSSEG6E8V, match_opcode, INSN_DREF },
+{"th.vssseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E16V, MASK_VSSSEG6E16V, match_opcode, INSN_DREF },
+{"th.vssseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E32V, MASK_VSSSEG6E32V, match_opcode, INSN_DREF },
+{"th.vssseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF },
+{"th.vlsseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG7BV, MASK_TH_VLSSEG7BV, match_opcode, INSN_DREF },
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+{"th.vlsseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E16V, MASK_VLSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vlsseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E32V, MASK_VLSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vlsseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vssseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E8V, MASK_VSSSEG7E8V, match_opcode, INSN_DREF },
+{"th.vssseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E16V, MASK_VSSSEG7E16V, match_opcode, INSN_DREF },
+{"th.vssseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E32V, MASK_VSSSEG7E32V, match_opcode, INSN_DREF },
+{"th.vssseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF },
+{"th.vlsseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8BV, MASK_TH_VLSSEG8BV, match_opcode, INSN_DREF },
+{"th.vlsseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8HV, MASK_TH_VLSSEG8HV, match_opcode, INSN_DREF },
+{"th.vlsseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_TH_VLSSEG8WV, MASK_TH_VLSSEG8WV, match_opcode, INSN_DREF },
+{"th.vlsseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E8V, MASK_VLSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vlsseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E16V, MASK_VLSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vlsseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vlsseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vssseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E8V, MASK_VSSSEG8E8V, match_opcode, INSN_DREF },
+{"th.vssseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E16V, MASK_VSSSEG8E16V, match_opcode, INSN_DREF },
+{"th.vssseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF },
+{"th.vssseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF },
+{"th.vlxseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2BV, MASK_TH_VLXSEG2BV, match_opcode, INSN_DREF },
+{"th.vlxseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2HV, MASK_TH_VLXSEG2HV, match_opcode, INSN_DREF },
+{"th.vlxseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG2WV, MASK_TH_VLXSEG2WV, match_opcode, INSN_DREF },
+{"th.vlxseg2bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg2hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI16V, MASK_VLOXSEG2EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg2wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI32V, MASK_VLOXSEG2EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg2b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg2h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI16V, MASK_VSOXSEG2EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg2w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI32V, MASK_VSOXSEG2EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg2e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3BV, MASK_TH_VLXSEG3BV, match_opcode, INSN_DREF },
+{"th.vlxseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3HV, MASK_TH_VLXSEG3HV, match_opcode, INSN_DREF },
+{"th.vlxseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG3WV, MASK_TH_VLXSEG3WV, match_opcode, INSN_DREF },
+{"th.vlxseg3bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI8V, MASK_VLOXSEG3EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg3hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI16V, MASK_VLOXSEG3EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg3wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI32V, MASK_VLOXSEG3EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg3b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI8V, MASK_VSOXSEG3EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg3h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI16V, MASK_VSOXSEG3EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg3w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI32V, MASK_VSOXSEG3EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg3e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4BV, MASK_TH_VLXSEG4BV, match_opcode, INSN_DREF },
+{"th.vlxseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4HV, MASK_TH_VLXSEG4HV, match_opcode, INSN_DREF },
+{"th.vlxseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG4WV, MASK_TH_VLXSEG4WV, match_opcode, INSN_DREF },
+{"th.vlxseg4bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI8V, MASK_VLOXSEG4EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg4hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI16V, MASK_VLOXSEG4EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg4wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI32V, MASK_VLOXSEG4EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg4b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI8V, MASK_VSOXSEG4EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg4h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI16V, MASK_VSOXSEG4EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg4w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI32V, MASK_VSOXSEG4EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg4e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5BV, MASK_TH_VLXSEG5BV, match_opcode, INSN_DREF },
+{"th.vlxseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5HV, MASK_TH_VLXSEG5HV, match_opcode, INSN_DREF },
+{"th.vlxseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG5WV, MASK_TH_VLXSEG5WV, match_opcode, INSN_DREF },
+{"th.vlxseg5bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI8V, MASK_VLOXSEG5EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg5hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI16V, MASK_VLOXSEG5EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg5wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI32V, MASK_VLOXSEG5EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg5b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI8V, MASK_VSOXSEG5EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg5h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI16V, MASK_VSOXSEG5EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg5w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI32V, MASK_VSOXSEG5EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg5e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6BV, MASK_TH_VLXSEG6BV, match_opcode, INSN_DREF },
+{"th.vlxseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6HV, MASK_TH_VLXSEG6HV, match_opcode, INSN_DREF },
+{"th.vlxseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG6WV, MASK_TH_VLXSEG6WV, match_opcode, INSN_DREF },
+{"th.vlxseg6bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI8V, MASK_VLOXSEG6EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg6hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI16V, MASK_VLOXSEG6EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg6wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI32V, MASK_VLOXSEG6EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg6b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI8V, MASK_VSOXSEG6EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg6h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI16V, MASK_VSOXSEG6EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg6w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI32V, MASK_VSOXSEG6EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg6e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7BV, MASK_TH_VLXSEG7BV, match_opcode, INSN_DREF },
+{"th.vlxseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7HV, MASK_TH_VLXSEG7HV, match_opcode, INSN_DREF },
+{"th.vlxseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG7WV, MASK_TH_VLXSEG7WV, match_opcode, INSN_DREF },
+{"th.vlxseg7bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI8V, MASK_VLOXSEG7EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg7hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI16V, MASK_VLOXSEG7EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg7wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI32V, MASK_VLOXSEG7EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg7b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI8V, MASK_VSOXSEG7EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg7h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI16V, MASK_VSOXSEG7EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg7w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI32V, MASK_VSOXSEG7EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg7e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF },
+{"th.vlxseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8BV, MASK_TH_VLXSEG8BV, match_opcode, INSN_DREF },
+{"th.vlxseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8HV, MASK_TH_VLXSEG8HV, match_opcode, INSN_DREF },
+{"th.vlxseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_TH_VLXSEG8WV, MASK_TH_VLXSEG8WV, match_opcode, INSN_DREF },
+{"th.vlxseg8bu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI8V, MASK_VLOXSEG8EI8V, match_opcode, INSN_DREF },
+{"th.vlxseg8hu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI16V, MASK_VLOXSEG8EI16V, match_opcode, INSN_DREF },
+{"th.vlxseg8wu.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF },
+{"th.vlxseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF },
+{"th.vsxseg8b.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI8V, MASK_VSOXSEG8EI8V, match_opcode, INSN_DREF },
+{"th.vsxseg8h.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI16V, MASK_VSOXSEG8EI16V, match_opcode, INSN_DREF },
+{"th.vsxseg8w.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF },
+{"th.vsxseg8e.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF },
+{"th.vlseg2bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2BFFV, MASK_TH_VLSEG2BFFV, match_opcode, INSN_DREF },
+{"th.vlseg2hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2HFFV, MASK_TH_VLSEG2HFFV, match_opcode, INSN_DREF },
+{"th.vlseg2wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG2WFFV, MASK_TH_VLSEG2WFFV, match_opcode, INSN_DREF },
+{"th.vlseg2buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg2huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E16FFV, MASK_VLSEG2E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg2wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E32FFV, MASK_VLSEG2E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg2eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg3bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3BFFV, MASK_TH_VLSEG3BFFV, match_opcode, INSN_DREF },
+{"th.vlseg3hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3HFFV, MASK_TH_VLSEG3HFFV, match_opcode, INSN_DREF },
+{"th.vlseg3wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG3WFFV, MASK_TH_VLSEG3WFFV, match_opcode, INSN_DREF },
+{"th.vlseg3buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg3huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E16FFV, MASK_VLSEG3E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg3wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E32FFV, MASK_VLSEG3E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg3eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg4bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4BFFV, MASK_TH_VLSEG4BFFV, match_opcode, INSN_DREF },
+{"th.vlseg4hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4HFFV, MASK_TH_VLSEG4HFFV, match_opcode, INSN_DREF },
+{"th.vlseg4wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG4WFFV, MASK_TH_VLSEG4WFFV, match_opcode, INSN_DREF },
+{"th.vlseg4buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E8FFV, MASK_VLSEG4E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg4huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E16FFV, MASK_VLSEG4E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg4wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E32FFV, MASK_VLSEG4E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg4eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg5bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5BFFV, MASK_TH_VLSEG5BFFV, match_opcode, INSN_DREF },
+{"th.vlseg5hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5HFFV, MASK_TH_VLSEG5HFFV, match_opcode, INSN_DREF },
+{"th.vlseg5wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG5WFFV, MASK_TH_VLSEG5WFFV, match_opcode, INSN_DREF },
+{"th.vlseg5buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E8FFV, MASK_VLSEG5E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg5huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E16FFV, MASK_VLSEG5E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg5wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E32FFV, MASK_VLSEG5E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg5eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg6bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6BFFV, MASK_TH_VLSEG6BFFV, match_opcode, INSN_DREF },
+{"th.vlseg6hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6HFFV, MASK_TH_VLSEG6HFFV, match_opcode, INSN_DREF },
+{"th.vlseg6wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG6WFFV, MASK_TH_VLSEG6WFFV, match_opcode, INSN_DREF },
+{"th.vlseg6buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E8FFV, MASK_VLSEG6E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg6huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E16FFV, MASK_VLSEG6E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg6wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E32FFV, MASK_VLSEG6E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg6eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg7bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7BFFV, MASK_TH_VLSEG7BFFV, match_opcode, INSN_DREF },
+{"th.vlseg7hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7HFFV, MASK_TH_VLSEG7HFFV, match_opcode, INSN_DREF },
+{"th.vlseg7wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG7WFFV, MASK_TH_VLSEG7WFFV, match_opcode, INSN_DREF },
+{"th.vlseg7buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E8FFV, MASK_VLSEG7E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg7huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E16FFV, MASK_VLSEG7E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg7wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg7eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF },
+{"th.vlseg8bff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8BFFV, MASK_TH_VLSEG8BFFV, match_opcode, INSN_DREF },
+{"th.vlseg8hff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8HFFV, MASK_TH_VLSEG8HFFV, match_opcode, INSN_DREF },
+{"th.vlseg8wff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_TH_VLSEG8WFFV, MASK_TH_VLSEG8WFFV, match_opcode, INSN_DREF },
+{"th.vlseg8buff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E8FFV, MASK_VLSEG8E8FFV, match_opcode, INSN_DREF },
+{"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF },
+{"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF },
+{"th.vlseg8eff.v",  0, INSN_CLASS_XTHEADVECTOR,  "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF },
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },