]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/mediatek: Fix XRGB setting error in OVL
authorHsiao Chien Sung <shawn.sung@mediatek.com>
Wed, 19 Jun 2024 16:38:43 +0000 (00:38 +0800)
committerChun-Kuang Hu <chunkuang.hu@kernel.org>
Thu, 20 Jun 2024 13:57:35 +0000 (13:57 +0000)
CONST_BLD must be enabled for XRGB formats although the alpha channel
can be ignored, or OVL will still read the value from memory.
This error only affects CRC generation.

Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20240620-igt-v3-3-a9d62d2e2c7e@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
drivers/gpu/drm/mediatek/mtk_disp_ovl.c

index b552a02d7eae7c71b37221b0fbf0d1a4c3cc8f11..bd00e5e85deba00fe67b898436328ad45325e81a 100644 (file)
@@ -38,6 +38,7 @@
 #define DISP_REG_OVL_PITCH_MSB(n)              (0x0040 + 0x20 * (n))
 #define OVL_PITCH_MSB_2ND_SUBBUF                       BIT(16)
 #define DISP_REG_OVL_PITCH(n)                  (0x0044 + 0x20 * (n))
+#define OVL_CONST_BLEND                                        BIT(28)
 #define DISP_REG_OVL_RDMA_CTRL(n)              (0x00c0 + 0x20 * (n))
 #define DISP_REG_OVL_RDMA_GMC(n)               (0x00c8 + 0x20 * (n))
 #define DISP_REG_OVL_ADDR_MT2701               0x0040
@@ -407,6 +408,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
        unsigned int fmt = pending->format;
        unsigned int offset = (pending->y << 16) | pending->x;
        unsigned int src_size = (pending->height << 16) | pending->width;
+       unsigned int ignore_pixel_alpha = 0;
        unsigned int con;
        bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
        union overlay_pitch {
@@ -428,6 +430,14 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
        if (state->base.fb && state->base.fb->format->has_alpha)
                con |= OVL_CON_AEN | OVL_CON_ALPHA;
 
+       /* CONST_BLD must be enabled for XRGB formats although the alpha channel
+        * can be ignored, or OVL will still read the value from memory.
+        * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+        * affect the result. Therefore we use !has_alpha as the condition.
+        */
+       if (state->base.fb && !state->base.fb->format->has_alpha)
+               ignore_pixel_alpha = OVL_CONST_BLEND;
+
        if (pending->rotation & DRM_MODE_REFLECT_Y) {
                con |= OVL_CON_VIRT_FLIP;
                addr += (pending->height - 1) * pending->pitch;
@@ -443,8 +453,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
 
        mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
                              DISP_REG_OVL_CON(idx));
-       mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
-                             DISP_REG_OVL_PITCH(idx));
+       mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | ignore_pixel_alpha,
+                             &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
        mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
                              DISP_REG_OVL_SRC_SIZE(idx));
        mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,