Fixes for 5.15

Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/queue-5.15/drm-connector-add-n-to-message-about-demoting-connec.patch b/queue-5.15/drm-connector-add-n-to-message-about-demoting-connec.patch
new file mode 100644 (file)
index 0000000..7975985
--- /dev/null
+++ b/queue-5.15/drm-connector-add-n-to-message-about-demoting-connec.patch
@@ -0,0 +1,39 @@
+From 0068c185e71e5cbe5f9f48ada1a2d34bc4b92ab3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 2 May 2024 15:32:35 -0700
+Subject: drm/connector: Add \n to message about demoting connector
+ force-probes
+
+From: Douglas Anderson <dianders@chromium.org>
+
+[ Upstream commit 6897204ea3df808d342c8e4613135728bc538bcd ]
+
+The debug print clearly lacks a \n at the end. Add it.
+
+Fixes: 8f86c82aba8b ("drm/connector: demote connector force-probes for non-master clients")
+Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
+Reviewed-by: Simon Ser <contact@emersion.fr>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240502153234.1.I2052f01c8d209d9ae9c300b87c6e4f60bd3cc99e@changeid
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/drm_connector.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
+index cfe163103cfd7..1140292820bb1 100644
+--- a/drivers/gpu/drm/drm_connector.c
++++ b/drivers/gpu/drm/drm_connector.c
+@@ -2460,7 +2460,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
+                                                    dev->mode_config.max_width,
+                                                    dev->mode_config.max_height);
+               else
+-                      drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe",
++                      drm_dbg_kms(dev, "User-space requested a forced probe on [CONNECTOR:%d:%s] but is not the DRM master, demoting to read-only probe\n",
+                                   connector->base.id, connector->name);
+       }
+ 
+-- 
+2.43.0
+

diff --git a/queue-5.15/drm-meson-dw-hdmi-add-bandgap-setting-for-g12.patch b/queue-5.15/drm-meson-dw-hdmi-add-bandgap-setting-for-g12.patch
new file mode 100644 (file)
index 0000000..9d67ba6
--- /dev/null
+++ b/queue-5.15/drm-meson-dw-hdmi-add-bandgap-setting-for-g12.patch
@@ -0,0 +1,135 @@
+From f2a8254987f8d1f1b2309e51f445439a91ba63f6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Apr 2024 18:02:54 +0200
+Subject: drm/meson: dw-hdmi: add bandgap setting for g12
+
+From: Jerome Brunet <jbrunet@baylibre.com>
+
+[ Upstream commit 08001033121dd92b8297a5b7333636b466c30f13 ]
+
+When no mode is set, the utility pin appears to be grounded. No signal
+is getting through.
+
+This is problematic because ARC and eARC use this line and may do so even
+if no display mode is set.
+
+This change enable the bandgap setting on g12 chip, which fix the problem
+with the utility pin. This is done by restoring init values on PHY init and
+disable.
+
+Fixes: 3b7c1237a72a ("drm/meson: Add G12A support for the DW-HDMI Glue")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20240426160256.3089978-3-jbrunet@baylibre.com
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240426160256.3089978-3-jbrunet@baylibre.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/meson/meson_dw_hdmi.c | 43 ++++++++++++++++-----------
+ 1 file changed, 26 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index f8dd22d6e6c62..2c8e978eb9ab9 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -105,6 +105,8 @@
+ #define HHI_HDMI_CLK_CNTL     0x1cc /* 0x73 */
+ #define HHI_HDMI_PHY_CNTL0    0x3a0 /* 0xe8 */
+ #define HHI_HDMI_PHY_CNTL1    0x3a4 /* 0xe9 */
++#define  PHY_CNTL1_INIT               0x03900000
++#define  PHY_INVERT           BIT(17)
+ #define HHI_HDMI_PHY_CNTL2    0x3a8 /* 0xea */
+ #define HHI_HDMI_PHY_CNTL3    0x3ac /* 0xeb */
+ #define HHI_HDMI_PHY_CNTL4    0x3b0 /* 0xec */
+@@ -129,6 +131,8 @@ struct meson_dw_hdmi_data {
+                                   unsigned int addr);
+       void            (*dwc_write)(struct meson_dw_hdmi *dw_hdmi,
+                                    unsigned int addr, unsigned int data);
++      u32 cntl0_init;
++      u32 cntl1_init;
+ };
+ 
+ struct meson_dw_hdmi {
+@@ -458,7 +462,9 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi,
+ 
+       DRM_DEBUG_DRIVER("\n");
+ 
+-      regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0);
++      /* Fallback to init mode */
++      regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, dw_hdmi->data->cntl1_init);
++      regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, dw_hdmi->data->cntl0_init);
+ }
+ 
+ static enum drm_connector_status dw_hdmi_read_hpd(struct dw_hdmi *hdmi,
+@@ -576,11 +582,22 @@ static const struct regmap_config meson_dw_hdmi_regmap_config = {
+       .fast_io = true,
+ };
+ 
+-static const struct meson_dw_hdmi_data meson_dw_hdmi_gx_data = {
++static const struct meson_dw_hdmi_data meson_dw_hdmi_gxbb_data = {
+       .top_read = dw_hdmi_top_read,
+       .top_write = dw_hdmi_top_write,
+       .dwc_read = dw_hdmi_dwc_read,
+       .dwc_write = dw_hdmi_dwc_write,
++      .cntl0_init = 0x0,
++      .cntl1_init = PHY_CNTL1_INIT | PHY_INVERT,
++};
++
++static const struct meson_dw_hdmi_data meson_dw_hdmi_gxl_data = {
++      .top_read = dw_hdmi_top_read,
++      .top_write = dw_hdmi_top_write,
++      .dwc_read = dw_hdmi_dwc_read,
++      .dwc_write = dw_hdmi_dwc_write,
++      .cntl0_init = 0x0,
++      .cntl1_init = PHY_CNTL1_INIT,
+ };
+ 
+ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
+@@ -588,6 +605,8 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data = {
+       .top_write = dw_hdmi_g12a_top_write,
+       .dwc_read = dw_hdmi_g12a_dwc_read,
+       .dwc_write = dw_hdmi_g12a_dwc_write,
++      .cntl0_init = 0x000b4242, /* Bandgap */
++      .cntl1_init = PHY_CNTL1_INIT,
+ };
+ 
+ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
+@@ -626,18 +645,8 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
+       meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
+ 
+       /* Setup PHY */
+-      regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                         0xffff << 16, 0x0390 << 16);
+-
+-      /* BIT_INVERT */
+-      if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
+-          dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
+-          dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
+-              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                                 BIT(17), 0);
+-      else
+-              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                                 BIT(17), BIT(17));
++      regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, meson_dw_hdmi->data->cntl1_init);
++      regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, meson_dw_hdmi->data->cntl0_init);
+ 
+       /* Enable HDMI-TX Interrupt */
+       meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
+@@ -866,11 +875,11 @@ static const struct dev_pm_ops meson_dw_hdmi_pm_ops = {
+ 
+ static const struct of_device_id meson_dw_hdmi_of_table[] = {
+       { .compatible = "amlogic,meson-gxbb-dw-hdmi",
+-        .data = &meson_dw_hdmi_gx_data },
++        .data = &meson_dw_hdmi_gxbb_data },
+       { .compatible = "amlogic,meson-gxl-dw-hdmi",
+-        .data = &meson_dw_hdmi_gx_data },
++        .data = &meson_dw_hdmi_gxl_data },
+       { .compatible = "amlogic,meson-gxm-dw-hdmi",
+-        .data = &meson_dw_hdmi_gx_data },
++        .data = &meson_dw_hdmi_gxl_data },
+       { .compatible = "amlogic,meson-g12a-dw-hdmi",
+         .data = &meson_dw_hdmi_g12a_data },
+       { }
+-- 
+2.43.0
+

diff --git a/queue-5.15/drm-meson-dw-hdmi-power-up-phy-on-device-init.patch b/queue-5.15/drm-meson-dw-hdmi-power-up-phy-on-device-init.patch
new file mode 100644 (file)
index 0000000..4f9f03f
--- /dev/null
+++ b/queue-5.15/drm-meson-dw-hdmi-power-up-phy-on-device-init.patch
@@ -0,0 +1,109 @@
+From b2d374ccb36b2105ab9a42eb176f5e197931e539 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 26 Apr 2024 18:02:53 +0200
+Subject: drm/meson: dw-hdmi: power up phy on device init
+
+From: Jerome Brunet <jbrunet@baylibre.com>
+
+[ Upstream commit 04703bfd7f99c016a823c74712b97f8b5590ce87 ]
+
+The phy is not in a useful state right after init. It will become useful,
+including for auxiliary function such as CEC or ARC, after the first mode
+is set. This is a problem on systems where the display is using another
+interface like DSI or CVBS.
+
+This change refactor the init and mode change callback to power up the PHY
+on init and leave only what is necessary for mode changes in the related
+function. This is enough to fix CEC operation when HDMI display is not
+enabled.
+
+Fixes: 3f68be7d8e96 ("drm/meson: Add support for HDMI encoder and DW-HDMI bridge + PHY")
+Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20240426160256.3089978-2-jbrunet@baylibre.com
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patchwork.freedesktop.org/patch/msgid/20240426160256.3089978-2-jbrunet@baylibre.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/gpu/drm/meson/meson_dw_hdmi.c | 51 +++++++++------------------
+ 1 file changed, 17 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+index 5cd2b2ebbbd33..f8dd22d6e6c62 100644
+--- a/drivers/gpu/drm/meson/meson_dw_hdmi.c
++++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c
+@@ -384,26 +384,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
+            drm_mode_is_420_also(display, mode)))
+               mode_is_420 = true;
+ 
+-      /* Enable clocks */
+-      regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, 0xffff, 0x100);
+-
+-      /* Bring HDMITX MEM output of power down */
+-      regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0);
+-
+-      /* Bring out of reset */
+-      dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_SW_RESET,  0);
+-
+-      /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
+-      dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
+-                             0x3, 0x3);
+-
+-      /* Enable cec_clk and hdcp22_tmdsclk_en */
+-      dw_hdmi_top_write_bits(dw_hdmi, HDMITX_TOP_CLK_CNTL,
+-                             0x3 << 4, 0x3 << 4);
+-
+-      /* Enable normal output to PHY */
+-      dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
+-
+       /* TMDS pattern setup */
+       if (mode->clock > 340000 && !mode_is_420) {
+               dw_hdmi->data->top_write(dw_hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01,
+@@ -425,20 +405,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
+       /* Setup PHY parameters */
+       meson_hdmi_phy_setup_mode(dw_hdmi, mode, mode_is_420);
+ 
+-      /* Setup PHY */
+-      regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                         0xffff << 16, 0x0390 << 16);
+-
+-      /* BIT_INVERT */
+-      if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
+-          dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
+-          dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
+-              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                                 BIT(17), 0);
+-      else
+-              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
+-                                 BIT(17), BIT(17));
+-
+       /* Disable clock, fifo, fifo_wr */
+       regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1, 0xf, 0);
+ 
+@@ -656,6 +622,23 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi)
+       meson_dw_hdmi->data->top_write(meson_dw_hdmi,
+                                      HDMITX_TOP_CLK_CNTL, 0xff);
+ 
++      /* Enable normal output to PHY */
++      meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));
++
++      /* Setup PHY */
++      regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
++                         0xffff << 16, 0x0390 << 16);
++
++      /* BIT_INVERT */
++      if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") ||
++          dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") ||
++          dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi"))
++              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
++                                 BIT(17), 0);
++      else
++              regmap_update_bits(priv->hhi, HHI_HDMI_PHY_CNTL1,
++                                 BIT(17), BIT(17));
++
+       /* Enable HDMI-TX Interrupt */
+       meson_dw_hdmi->data->top_write(meson_dw_hdmi, HDMITX_TOP_INTR_STAT_CLR,
+                                      HDMITX_TOP_INTR_CORE);
+-- 
+2.43.0
+

diff --git a/queue-5.15/series b/queue-5.15/series
index 19cc503ad6b27cbabbb6231e525d164e0e5a1ce7..dde9e0f171c947e42f10c0f72e7328a8f3531c79 100644 (file)
--- a/queue-5.15/series
+++ b/queue-5.15/series
@@ -135,3 +135,6 @@ net-hns3-change-type-of-numa_node_mask-as-nodemask_t.patch
 net-hns3-use-appropriate-barrier-function-after-sett.patch
 net-hns3-split-function-hclge_init_vlan_config.patch
 net-hns3-fix-port-vlan-filter-not-disabled-issue.patch
+drm-meson-dw-hdmi-power-up-phy-on-device-init.patch
+drm-meson-dw-hdmi-add-bandgap-setting-for-g12.patch
+drm-connector-add-n-to-message-about-demoting-connec.patch