drm/amd: Update `update_pcie_parameters` functions to use uint8_t arguments

The matching values for `pcie_gen_cap` and `pcie_width_cap` when
fetched from powerplay tables are 1 byte, so narrow the arguments
to match to ensure min() and max() comparisons without casts.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 33eaf0d77163f2b5a4cde5d1ca45d7b274c4a45c..99750c1822794b9b2f325f8ff82f8b2055058236 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1270,7 +1270,7 @@ static int smu_smc_hw_setup(struct smu_context *smu)
 {
        struct smu_feature *feature = &smu->smu_feature;
        struct amdgpu_device *adev = smu->adev;
-       uint32_t pcie_gen = 0, pcie_width = 0;
+       uint8_t pcie_gen = 0, pcie_width = 0;
        uint64_t features_supported;
        int ret = 0;
 

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 4f6df3558b9b393644e03b992d103cf80fe25787..f3cab5e633a779fbed149d4806abd954efacacf1 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -846,7 +846,7 @@ struct pptable_funcs {
         * &pcie_gen_cap: Maximum allowed PCIe generation.
         * &pcie_width_cap: Maximum allowed PCIe width.
         */
-       int (*update_pcie_parameters)(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap);
+       int (*update_pcie_parameters)(struct smu_context *smu, uint8_t pcie_gen_cap, uint8_t pcie_width_cap);
 
        /**
         * @i2c_init: Initialize i2c.

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 355c156d871aff86aff1c64d8bc1278c14ea9cbb..cc02f979e9e9843e10d2fd0ca3c6764cb2cdf91f 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -296,8 +296,8 @@ int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
                                        uint32_t pptable_id);
 
 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
-                                    uint32_t pcie_gen_cap,
-                                    uint32_t pcie_width_cap);
+                                    uint8_t pcie_gen_cap,
+                                    uint8_t pcie_width_cap);
 
 #endif
 #endif

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 650482cedd1f05c7bce022b8ac9979bc38b5aa00..5f3cbfff156ae1dc9ea0f3434a843321089377ef 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2380,8 +2380,8 @@ static int navi10_get_power_limit(struct smu_context *smu,
 }
 
 static int navi10_update_pcie_parameters(struct smu_context *smu,
-                                    uint32_t pcie_gen_cap,
-                                    uint32_t pcie_width_cap)
+                                        uint8_t pcie_gen_cap,
+                                        uint8_t pcie_width_cap)
 {
        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
        PPTable_t *pptable = smu->smu_table.driver_pptable;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 1f05bfb7d473cdcd7046ec24193916ead628b3a2..dd07662262e47a0ce734101d95e6821f2df54684 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2092,14 +2092,14 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context
 #define MAX(a, b)      ((a) > (b) ? (a) : (b))
 
 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
-                                        uint32_t pcie_gen_cap,
-                                        uint32_t pcie_width_cap)
+                                                uint8_t pcie_gen_cap,
+                                                uint8_t pcie_width_cap)
 {
        struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
        struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table;
        uint8_t *table_member1, *table_member2;
-       uint32_t min_gen_speed, max_gen_speed;
-       uint32_t min_lane_width, max_lane_width;
+       uint8_t min_gen_speed, max_gen_speed;
+       uint8_t min_lane_width, max_lane_width;
        uint32_t smu_pcie_arg;
        int ret, i;
 

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 8d1e39589057fb7869c5a2d8ad359811f1647082..5965bd8b0dfa909c1096e5f514c06973bc7be832 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2420,8 +2420,8 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
 }
 
 int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
-                                    uint32_t pcie_gen_cap,
-                                    uint32_t pcie_width_cap)
+                                    uint8_t pcie_gen_cap,
+                                    uint8_t pcie_width_cap)
 {
        struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
        struct smu_13_0_pcie_table *pcie_table =