net: phy: introduce core support for phy-mode = "10g-qxgmii"

10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
specification. It uses the same signaling as USXGMII, but it multiplexes
4 ports over the link, resulting in a maximum speed of 2.5G per port.

Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
they could get away just fine with that thus far. But there is a need to
distinguish between the 2 as far as SerDes drivers are concerned.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
index 1283240d7620bd88fc7af11685752ab023686e43..f64641417c541f746115cad2128b770126397999 100644 (file)
--- a/Documentation/networking/phy.rst
+++ b/Documentation/networking/phy.rst
@@ -327,6 +327,12 @@ Some of the interface modes are described below:
     This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
     SGMII lines into a single link compared to 4 on QSGMII.
 
+``PHY_INTERFACE_MODE_10G_QXGMII``
+    Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
+    Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz
+    SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
+    through symbol replication. The PCS expects the standard USXGMII code word.
+
 Pause frames / flow control
 ===========================
 

diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
index 15f349e5995a68d4e302bf26db0f141eba439cfa..a235ea2264a7febce9f4891f6770a75e326b526b 100644 (file)
--- a/drivers/net/phy/phy-core.c
+++ b/drivers/net/phy/phy-core.c
@@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface)
                return 1;
        case PHY_INTERFACE_MODE_QSGMII:
        case PHY_INTERFACE_MODE_QUSGMII:
+       case PHY_INTERFACE_MODE_10G_QXGMII:
                return 4;
        case PHY_INTERFACE_MODE_PSGMII:
                return 5;

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 02427378acfda1e9b6faeda242a80887da37bee1..6c24c48dcf0f4eca4135b5afcd0beb9e4ea1fc94 100644 (file)
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface)
                return SPEED_1000;
 
        case PHY_INTERFACE_MODE_2500BASEX:
+       case PHY_INTERFACE_MODE_10G_QXGMII:
                return SPEED_2500;
 
        case PHY_INTERFACE_MODE_5GBASER:
@@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface,
 
        switch (interface) {
        case PHY_INTERFACE_MODE_USXGMII:
-               caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
+               caps |= MAC_10000FD | MAC_5000FD;
+               fallthrough;
+
+       case PHY_INTERFACE_MODE_10G_QXGMII:
+               caps |= MAC_2500FD;
                fallthrough;
 
        case PHY_INTERFACE_MODE_RGMII_TXID:
@@ -926,6 +931,7 @@ static int phylink_parse_mode(struct phylink *pl,
                case PHY_INTERFACE_MODE_5GBASER:
                case PHY_INTERFACE_MODE_25GBASER:
                case PHY_INTERFACE_MODE_USXGMII:
+               case PHY_INTERFACE_MODE_10G_QXGMII:
                case PHY_INTERFACE_MODE_10GKR:
                case PHY_INTERFACE_MODE_10GBASER:
                case PHY_INTERFACE_MODE_XLGMII:
@@ -1124,6 +1130,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode,
        case PHY_INTERFACE_MODE_QSGMII:
        case PHY_INTERFACE_MODE_QUSGMII:
        case PHY_INTERFACE_MODE_USXGMII:
+       case PHY_INTERFACE_MODE_10G_QXGMII:
                /* These protocols are designed for use with a PHY which
                 * communicates its negotiation result back to the MAC via
                 * inband communication. Note: there exist PHYs that run

diff --git a/include/linux/phy.h b/include/linux/phy.h
index e6e83304558e07b1133b42302261639068e192b3..205fccfc0f60a0b55693d161898f4d4b51072280 100644 (file)
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -128,6 +128,7 @@ extern const int phy_10gbit_features_array[1];
  * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
  * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
  * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
+ * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
  * @PHY_INTERFACE_MODE_MAX: Book keeping
  *
  * Describes the interface between the MAC and PHY.
@@ -168,6 +169,7 @@ typedef enum {
        PHY_INTERFACE_MODE_10GKR,
        PHY_INTERFACE_MODE_QUSGMII,
        PHY_INTERFACE_MODE_1000BASEKX,
+       PHY_INTERFACE_MODE_10G_QXGMII,
        PHY_INTERFACE_MODE_MAX,
 } phy_interface_t;
 
@@ -289,6 +291,8 @@ static inline const char *phy_modes(phy_interface_t interface)
                return "100base-x";
        case PHY_INTERFACE_MODE_QUSGMII:
                return "qusgmii";
+       case PHY_INTERFACE_MODE_10G_QXGMII:
+               return "10g-qxgmii";
        default:
                return "unknown";
        }

diff --git a/include/linux/phylink.h b/include/linux/phylink.h
index a30a692acc327dbf08485766dcd535cc9bbe9b48..2381e07429a28defcc6ae81d0b84eb7cb437c260 100644 (file)
--- a/include/linux/phylink.h
+++ b/include/linux/phylink.h
@@ -654,6 +654,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface)
        case PHY_INTERFACE_MODE_SGMII:
        case PHY_INTERFACE_MODE_QSGMII:
        case PHY_INTERFACE_MODE_USXGMII:
+       case PHY_INTERFACE_MODE_10G_QXGMII:
                return 1600000;
 
        case PHY_INTERFACE_MODE_1000BASEX: