pinctrl: renesas: r8a779g0: Fix CANFD5 suffix

CAN-FD instance 5 has two alternate pin groups: "canfd5" and "canfd5_b".
Rename the former to "canfd5_a" to increase uniformity.

While at it, remove the unneeded separator.

Fixes: ad9bb2fec66262b0 ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support")
Fixes: 050442ae4c74f830 ("pinctrl: renesas: r8a779g0: Add pins, groups and functions")
Fixes: c2b4b2cd632d17e7 ("pinctrl: renesas: r8a779g0: Add missing CANFD5_B")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/10b22d54086ed11cdfeb0004583029ccf249bdb9.1717754960.git.geert+renesas@glider.be

diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index d2de526a3b588689299a6cf9c01ce7c1a28dc538..d90ba8b6b4b423ed783bb97caf39db868f493f28 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -341,8 +341,8 @@
 /* IP0SR2 */           /* 0 */                 /* 1 */                 /* 2 */                 /* 3            4        5        6        7        8        9        A        B        C        D        E        F */
 #define IP0SR2_3_0     FM(FXR_TXDA)            FM(CANFD1_TX)           FM(TPU0TO2_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_7_4     FM(FXR_TXENA_N)         FM(CANFD1_RX)           FM(TPU0TO3_A)           F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX)           FM(IRQ5)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX)           FM(IRQ4_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_11_8    FM(RXDA_EXTFXR)         FM(CANFD5_TX_A)         FM(IRQ5)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12   FM(CLK_EXTFXR)          FM(CANFD5_RX_A)         FM(IRQ4_B)              F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_19_16   FM(RXDB_EXTFXR)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_23_20   FM(FXR_TXENB_N)         F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0SR2_27_24   FM(FXR_TXDB)            F_(0, 0)                F_(0, 0)                F_(0, 0)        F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -896,11 +896,11 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_GPSR(IP0SR2_7_4,    TPU0TO3_A),
 
        PINMUX_IPSR_GPSR(IP0SR2_11_8,   RXDA_EXTFXR),
-       PINMUX_IPSR_GPSR(IP0SR2_11_8,   CANFD5_TX),
+       PINMUX_IPSR_GPSR(IP0SR2_11_8,   CANFD5_TX_A),
        PINMUX_IPSR_GPSR(IP0SR2_11_8,   IRQ5),
 
        PINMUX_IPSR_GPSR(IP0SR2_15_12,  CLK_EXTFXR),
-       PINMUX_IPSR_GPSR(IP0SR2_15_12,  CANFD5_RX),
+       PINMUX_IPSR_GPSR(IP0SR2_15_12,  CANFD5_RX_A),
        PINMUX_IPSR_GPSR(IP0SR2_15_12,  IRQ4_B),
 
        PINMUX_IPSR_GPSR(IP0SR2_19_16,  RXDB_EXTFXR),
@@ -1531,15 +1531,14 @@ static const unsigned int canfd4_data_mux[] = {
 };
 
 /* - CANFD5 ----------------------------------------------------------------- */
-static const unsigned int canfd5_data_pins[] = {
-       /* CANFD5_TX, CANFD5_RX */
+static const unsigned int canfd5_data_a_pins[] = {
+       /* CANFD5_TX_A, CANFD5_RX_A */
        RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
 };
-static const unsigned int canfd5_data_mux[] = {
-       CANFD5_TX_MARK, CANFD5_RX_MARK,
+static const unsigned int canfd5_data_a_mux[] = {
+       CANFD5_TX_A_MARK, CANFD5_RX_A_MARK,
 };
 
-/* - CANFD5_B ----------------------------------------------------------------- */
 static const unsigned int canfd5_data_b_pins[] = {
        /* CANFD5_TX_B, CANFD5_RX_B */
        RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
@@ -2578,8 +2577,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(canfd2_data),
        SH_PFC_PIN_GROUP(canfd3_data),
        SH_PFC_PIN_GROUP(canfd4_data),
-       SH_PFC_PIN_GROUP(canfd5_data),          /* suffix might be updated */
-       SH_PFC_PIN_GROUP(canfd5_data_b),        /* suffix might be updated */
+       SH_PFC_PIN_GROUP(canfd5_data_a),
+       SH_PFC_PIN_GROUP(canfd5_data_b),
        SH_PFC_PIN_GROUP(canfd6_data),
        SH_PFC_PIN_GROUP(canfd7_data),
        SH_PFC_PIN_GROUP(can_clk),
@@ -2788,8 +2787,7 @@ static const char * const canfd4_groups[] = {
 };
 
 static const char * const canfd5_groups[] = {
-       /* suffix might be updated */
-       "canfd5_data",
+       "canfd5_data_a",
        "canfd5_data_b",
 };