MIPS: Sync icache for whole exception vector

Rather than performing cache flushing for a fixed 0x400 bytes, use the
actual size of the vector in order to ensure we cover all emitted code
on systems that make use of vectored interrupts.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Cc: linux-mips@vger.kernel.org

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 9b565ed5166225817f1f4fe397a4722e3fde65c1..2775190adbe7e580f9ab771bfa1fcd974ca5a029 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2454,7 +2454,7 @@ void __init trap_init(void)
        else
                set_handler(0x080, &except_vec3_generic, 0x80);
 
-       local_flush_icache_range(ebase, ebase + 0x400);
+       local_flush_icache_range(ebase, ebase + vec_size);
 
        sort_extable(__start___dbe_table, __stop___dbe_table);