net: sh_eth: arm: renesas: README: Drop CFG_SH_ETHER_CACHE_*

Drop CFG_SH_ETHER_CACHE_WRITEBACK and CFG_SH_ETHER_CACHE_INVALIDATE,
which are now always enabled in the sh_eth driver, because those cache
operations are always available. On architectures which do not implement
cache operations yet, cache operations have to be implemented first.

CFG_SH_ETHER_ALIGNE_SIZE now set as SH_ETHER_ALIGN_SIZE in sh_eth.h
based on architecture and no longer configured on board level.

Remove CFG_SH_ETHER_CACHE_WRITEBACK configuration option from README.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/README b/README
index 8f8f4b85ef80c500ecb5f616e569f86497ff1001..7acf39540c2b253cca2aa9392df5d36483c434ad 100644 (file)
--- a/README
+++ b/README
@@ -382,9 +382,6 @@ The following options need to be configured:
                        CFG_SH_ETHER_PHY_ADDR
                        Define the ETH PHY's address
 
-                       CFG_SH_ETHER_CACHE_WRITEBACK
-                       If this option is set, the driver enables cache flush.
-
 - TPM Support:
                CONFIG_TPM
                Support TPM devices.

diff --git a/include/configs/alt.h b/include/configs/alt.h
index 52b8c95cd7ba7aba700e1a0c55b03115565f9f43..987fd25bb4c59a9798db539aa417fa11d291dfcd 100644 (file)
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -23,9 +23,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/condor.h b/include/configs/condor.h
index ecaf58e4c0f98aae8a8d9de0a45917ae014bde64..b2d66c785fc7fb332738806f25a88dad29c2f486 100644 (file)
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -16,9 +16,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */

diff --git a/include/configs/gose.h b/include/configs/gose.h
index 323977e9b8a617592da54aab688d38dfb5323481..acef925855a35407aaeaac46fdb615ff292b1183 100644 (file)
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -22,9 +22,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h
index 67ad83398169c4a4e7be4e447fa310f2524cd21b..9a7eef57c876157ff07b0893ae1e47993c36e50a 100644 (file)
--- a/include/configs/grpeach.h
+++ b/include/configs/grpeach.h
@@ -19,8 +19,5 @@
 /* Network interface */
 #define CFG_SH_ETHER_PHY_ADDR  0
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 #endif /* __GRPEACH_H */

diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 11f637d3f337e70570dcf445eea34f57ba8451bb..13d2127ac13578f9e19c7b03ba1229af657b506f 100644 (file)
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -22,9 +22,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/lager.h b/include/configs/lager.h
index aaf4a4a69313626c55fd083847e1a93436397b46..d76f003e391c9705c5d04d6b04e3c25036a3884d 100644 (file)
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -23,9 +23,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/porter.h b/include/configs/porter.h
index ff99c3fb8177d82af894247d2f39ce4c106ebc48..eaf5d31c1d3672a090f1f7d17c7e7d5a1083445c 100644 (file)
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -24,9 +24,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/silk.h b/include/configs/silk.h
index 20d18aa5aa73530745da9ae286ec5cf922ddbaa5..4ef70281ddaf82c3f0e88d354fe9c4220449cc8b 100644 (file)
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -24,9 +24,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/stout.h b/include/configs/stout.h
index 454d8ca571649de6a81303138985383bca37d872..cb544de243e7d2a88b79edceed79a18a6f34b203 100644 (file)
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -28,9 +28,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x1
 #define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 

diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h
index e16a289ac1a8c602913f3038ac8ac9741920e511..a8d1641b36ea5b4aa9bd55f0b603b592d194a921 100644 (file)
--- a/include/configs/v3hsk.h
+++ b/include/configs/v3hsk.h
@@ -17,9 +17,6 @@
 /* SH Ether */
 #define CFG_SH_ETHER_PHY_ADDR  0x0
 #define CFG_SH_ETHER_PHY_MODE  PHY_INTERFACE_MODE_RGMII_ID
-#define CFG_SH_ETHER_CACHE_WRITEBACK
-#define CFG_SH_ETHER_CACHE_INVALIDATE
-#define CFG_SH_ETHER_ALIGNE_SIZE       64
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */