drm/amd/display: Optimize cursor position updates

[why]
Updating the cursor enablement register can be a slow operation and accumulates
when high polling rate cursors cause frequent updates asynchronously to the
cursor position.

[how]
Since the cursor enable bit is cached there is no need to update the
enablement register if there is no change to it.  This removes the
read-modify-write from the cursor position programming path in HUBP and
DPP, leaving only the register writes.

Reviewed-by: Josip Pavic <josip.pavic@amd.com>
Signed-off-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
index e1da48b05d0094a103f6dfbefe7bf736a26fcfd4..8f6529a98f31fc04b06dc50f06d62e9617fe6de9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c
@@ -480,10 +480,11 @@ void dpp1_set_cursor_position(
        if (src_y_offset + cursor_height <= 0)
                cur_en = 0;  /* not visible beyond top edge*/
 
-       REG_UPDATE(CURSOR0_CONTROL,
-                       CUR0_ENABLE, cur_en);
+       if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
+               REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
 
-       dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
+               dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
+       }
 }
 
 void dpp1_cnv_set_optional_cursor_attributes(

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
index 3b6ca7974e188df5ed8bd7579fd416acd12e950e..1236e0f9a2560cbf87894adddb5faac817da4292 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c
@@ -154,9 +154,11 @@ void dpp401_set_cursor_position(
        struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
        uint32_t cur_en = pos->enable ? 1 : 0;
 
-       REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
+       if (dpp_base->pos.cur0_ctl.bits.cur0_enable != cur_en) {
+               REG_UPDATE(CURSOR0_CONTROL, CUR0_ENABLE, cur_en);
 
-       dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
+               dpp_base->pos.cur0_ctl.bits.cur0_enable = cur_en;
+       }
 }
 
 void dpp401_set_optional_cursor_attributes(

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index c74f6a3313a27c470feebe92ca294afe875c1f27..d537d0c53cf0311a18b0818ac9a5e70033f277ca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -1058,11 +1058,13 @@ void hubp2_cursor_set_position(
        if (src_y_offset + cursor_height <= 0)
                cur_en = 0;  /* not visible beyond top edge*/
 
-       if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
-               hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
+       if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
+               if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
+                       hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
 
-       REG_UPDATE(CURSOR_CONTROL,
+               REG_UPDATE(CURSOR_CONTROL,
                        CURSOR_ENABLE, cur_en);
+       }
 
        REG_SET_2(CURSOR_POSITION, 0,
                        CURSOR_X_POSITION, pos->x,

diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
index d38e3f3a1107c09b9edebb318b261528acf793c8..3595c74a3a2fb9bacbc7ced3b9751718fb510015 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn401/dcn401_hubp.c
@@ -730,11 +730,13 @@ void hubp401_cursor_set_position(
                        dc_fixpt_from_int(dst_x_offset),
                        param->h_scale_ratio));
 
-       if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
-               hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
+       if (hubp->pos.cur_ctl.bits.cur_enable != cur_en) {
+               if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
+                       hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
 
-       REG_UPDATE(CURSOR_CONTROL,
-               CURSOR_ENABLE, cur_en);
+               REG_UPDATE(CURSOR_CONTROL,
+                       CURSOR_ENABLE, cur_en);
+       }
 
        REG_SET_2(CURSOR_POSITION, 0,
                CURSOR_X_POSITION, x_pos,